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參數(shù)資料
| 型號： | SI5017-D-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 4/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 28MLP |
| 標準包裝： | 60 |
| 系列： | DSPLL® |
| 類型： | 時鐘和數(shù)據(jù)恢復（CDR） |
| PLL： | 是 |
| 主要目的： | SONET/SDH，ATM 應用 |
| 輸入： | 時鐘 |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.7GHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 28-MLP-EP（5x5） |
| 包裝： | 管件 |
| 其它名稱： | 336-1279 |
Si5017
12
Rev. 1.5
4. Functional Description
The Si5017 integrates a high-speed limiting amplifier
with a CDR unit that operates between 2.4 and
2.7 Gbps. No external reference clock is required for
clock and data recovery. The limiting amplifier magnifies
very low-level input data signals so accurate clock and
data recovery can be performed. The CDR uses Silicon
Laboratories DSPLL technology to recover a clock
synchronous to the input data stream. The recovered
clock retimes the incoming data, and both are output
synchronously via current-mode logic (CML) drivers.
Silicon Laboratories’ DSPLL technology ensures
superior jitter performance while eliminating the need
for external loop filter components found in traditional
phase-locked loop (PLL) implementations.
The limiting amplifier includes a control input for
adjusting the data slicing level and provides a loss-of-
signal level alarm output. The CDR includes a bit-error-
rate performance monitor which signals a high bit-error-
rate condition (associated with excessive incoming
jitter) relative to an externally adjustable bit-error-rate
threshold.
The optional reference clock minimizes the CDR
acquisition time and provides a stable reference for
maintaining the output clock when locking to reference
is desired.
4.1. Limiting Amplifier
The limiting amplifier accepts the low-level signal output
from a transimpedance amplifier (TIA). The low-level
signal is amplified to a usable level for the CDR unit.
The minimum input swing requirement is specified in
Table 2. Larger input amplitudes (up to the maximum
input swing specified in Table 2) are accommodated
without degradation of performance. The limiting
amplifier ensures optimal data slicing by using a digital
dc offset cancellation technique to remove any dc bias
introduced by the amplification stage.
4.2. DSPLL
The Si5017 PLL structure (shown in the "1. Detailed
Block Diagram" on page 4) utilizes Silicon Laboratories'
DSPLL
technology
to
maintain
superior
jitter
performance while eliminating the need for external loop
filter
components
found
in
traditional
PLL
implementations. This is achieved using a digital signal
processing (DSP) algorithm to replace the loop filter
commonly found in analog PLL designs. This algorithm
processes the phase detector error term and generates
a digital control value to adjust the frequency of the
voltage-controlled oscillator (VCO). This technology
enables CDR with far less jitter than is generated using
traditional methods, and it eliminates performance
degradation caused by external component aging. In
addition, because external loop filter components are
not required, sensitive noise entry points are eliminated,
thus making the DSPLL less susceptible to board-level
noise
sources
and
making
SONET/SDH
jitter
compliance easier to attain in the application.
4.3. Operation Without an External Refer-
ence
The Si5017 can perform clock and data recovery
without an external reference clock. Tying the
REFCLK+ input to VDD and the REFCLK– input to
GND configures the device to operate without an
external reference clock. Clock recovery is achieved by
monitoring the timing quality of the incoming data
relative to the VCO frequency. Lock is maintained by
continuously monitoring the incoming data timing quality
and adjusting the VCO accordingly. Details of the lock
detection and the lock-to-reference functions while in
this mode are described in their respective sections
below.
Note: Without an external reference the acquisition of data is
dependent solely on the data itself and typically
requires more time to acquire lock than when a refer-
ence is applied.
4.4. Operation With an External Reference
The Si5017 can also perform clock and data recovery
with an external reference. The device’s optional
external reference clock centers the DSPLL, minimizes
the acquisition time, and maintains a stable output clock
(CLKOUT) when lock-to-reference (LTR) is asserted.
When the reference clock is present, the Si5017 uses
the reference clock to center the VCO output frequency
so that clock and data are recovered from the input data
stream. The device self configures for operation with
one of three reference clock frequencies. This
eliminates the need to externally configure the device to
operate with a particular reference clock.
The reference clock centers the VCO for a nominal
output between 2.5 and 2.7 GHz. The VCO frequency is
centered at 16, 32, or 128 times the reference clock
frequency. Detection circuitry continuously monitors the
reference clock input to determine whether the device
should be configured for a reference clock that is 1/16,
1/32, or 1/128 the nominal VCO output. Approximate
reference clock frequencies for some target applications
are given in Table 7.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SI5017-D-GMR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 OC48/STM16 CDR FEC RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5017-EVB | 功能描述:時鐘和定時器開發(fā)工具 OC48 STM16 SNT/SDH 2.7Gbps w/ limit amp RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| SI5017-X-GM | 制造商:SILABS 制造商全稱:SILABS 功能描述:OC-48/STM-16 SONET/SDH CDR IC WITH LIMITING AMPLIFIER |
| SI5018 | 制造商:SILABS 制造商全稱:SILABS 功能描述:SiPHY⑩ OC-48/STM-16 CLOCK AND DATA RECOVERY IC WITH FEC |
| SI-50182 | 制造商:BEL 制造商全稱:Bel Fuse Inc. 功能描述:SI-50182 |
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