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Si5017
9
Rev. 1.5
Table 4. AC Characteristics (PLL Characteristics)
(VDD =3.3 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Jitter Tolerance
(OC-48)*
JTOL(PP)
f = 600 Hz
40
—
UIPP
f = 6000 Hz
4
—
UIPP
f = 100 kHz
3
—
UIPP
f = 1 MHz
0.3
—
UIPP
RMS Jitter Generation*
JGEN(rms) with no jitter on serial data
—
3.0
5.0
mUI
Peak-to-Peak Jitter Generation*
JGEN(PP)
with no jitter on serial data
—
25
55
mUI
Jitter Transfer Bandwidth*
JBW
OC-48
—
2.0
MHz
Jitter Transfer Peaking*
JP
—0.03
0.1
dB
Acquisition Time
(Reference clock applied)
TAQ
After falling edge of
RESET/CAL
—1.6
2.2
ms
From the return of valid
data
20
100
500
s
Acquisition Time
(Reference-less operation)
TAQ
After falling edge of
RESET/CAL
—2.0
5.5
ms
From the return of valid
data
1.5
2.5
5.5
ms
Reference Clock Range
fCLK / 16
fCLK / 32
fCLK / 128
—
155.52
77.76
19.44
—
MHz
Input Reference Clock Frequency
Tolerance
CTOL
–500
—
+500
ppm
Frequency Difference at which
Receive PLL goes out of Lock
(REFCLK compared to the divided
down VCO clock)
—±650
—
ppm
*Note: As defined in Bellcore specifications: GR-253-CORE, Issue 3, September 2000. Using PRBS 223 – 1 data pattern.