參數(shù)資料
型號(hào): SI3050-E1-GT
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 90/128頁(yè)
文件大小: 0K
描述: IC VOICE DAA SYSTEM SIDE 24QFN
標(biāo)準(zhǔn)包裝: 74
系列: *
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Si3050 + Si3011/18/19
64
Rev. 1.5
Reset settings = 0000_0011
Register 2. Control 2
Bit
D7D6D5
D4
D3
D2
D1D0
Name
INTE
INTP
WDTEN
RDI
HBE
RXE
Type
R/W
Bit
Name
Function
7INTE
Interrupt Pin Enable.
0=The AOUT/INT pin functions as an analog output for call progress monitoring purposes.
1=The AOUT/INT pin functions as a hardware interrupt pin.
6INTP
Interrupt Polarity Select.
0=The AOUT/INT pin, when used in hardware interrupt mode, is active low.
1=The AOUT/INT pin, when used in hardware interrupt mode, is active high.
5
Reserved
Read returns zero.
4WDTEN
Watchdog Timer Enable.
0 = Watchdog timer disabled.
1 = Watchdog timer enabled. When set, this bit can be cleared only by a hardware reset. The
watchdog timer monitors register access. If no register access occurs within a 4 s window, the
DAA is put into an on-hook state. A read or write of a DAA register restarts the watchdog timer
counter. If the watchdog timer times out, the OH bit is cleared, placing the DAA into an
on-hook state. Setting the OH bit places the DAA back into an off-hook state.
3
Reserved
Read returns zero.
2RDI
Ring Detect Interrupt Mode.
This bit operates in conjunction with the RDTM and RDTI bits. This bit selects whether one or
two interrupts are generated for every ring burst.
0 = An interrupt is generated at the beginning of every ring burst.
1 = An interrupt is generated at the beginning and end of every ring burst. The interrupt at the
beginning of the ring burst must be serviced (by writing 0 to the RDTI bit) before the end of the
ring burst in order for both interrupts to occur.
1HBE
Hybrid Enable.
0 = Disconnects hybrid in transmit path.
1 = Connects hybrid in transmit path.
0RXE
Receive Enable.
0 = Receive path disabled.
1 = Enables receive path.
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