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| 型號： | sda 9254-2 |
| 廠商： | SIEMENS AG |
| 英文描述： | 2.6 MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM) with On-chip Noise Reduction Filter(應(yīng)用于TV的2.6 M位動態(tài)存儲器) |
| 中文描述： | 2.6兆比特的動態(tài)影視順序訪問應(yīng)用程序的內(nèi)存（電視，SAM）的具有片上降噪過濾器（應(yīng)用于電視的260萬位動態(tài)存儲器） |
| 文件頁數(shù)： | 5/32頁 |
| 文件大?。?/td> | 182K |
| 代理商： | SDA 9254-2 |
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SDA 9254-2
Semiconductor Group
5
1998-01-16
The following diagram shows the requested data format for 4:1:1 signals at the input
SDC0 … SDC11. The output data format at pins SQA0 … SQA11 corresponds to the input format.
Figure 4
Input Data Format (4:1:1)
Memory
The memory has a capacity of 2605056 bit. It is organized as 212 rows by 64 columns by 16 arrays
by 12 bit and allows the storage of the active part of a complete 4:1:1-TV field using a 13.5 MHz
sample rate. The memory is fabricated using the same CMOS technology used for 4-Mbit standard
dynamic random access memories.
The extremely high maximum data rate is achieved by three internal shift registers, each of 16-bit
length and 12-bit width, which perform a serial to parallel conversion between the asynchronous
input/output data streams and the memory array. The parallel data transfer from the 16 x 12-bit input
shift register C to an addressed location of the memory array and from the memory array to one of
the 16 x 12-bit output shift registers A or B is controlled by the serial row-(SAR) and column address
(SAC) which contains the desired column address and an instruction code (mode bits) for transfer
and refresh.
Y1
Y2
Y3
Y4
Y5
Y6
U2,7
U1,7
U1,5
U1,3
U1,1
U2,5
U2,6
U1,6
U1,4
U1,2
U1,0
U2,4
V2,7
V1,7
V1,5
V1,3
V1,1
V2,5
V2,6
V1,6
V1,4
V1,2
V1,0
V2,4
BLN
13.5 MHz
SDC 4 ... 11
SDC 3
SDC 2
SDC 1
SDC 0
UED08600
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| SDA9254-2 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.6 MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM) with On-chip Noise Reduction Filter |
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