參數(shù)資料
型號(hào): sda 9254-2
廠商: SIEMENS AG
英文描述: 2.6 MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM) with On-chip Noise Reduction Filter(應(yīng)用于TV的2.6 M位動(dòng)態(tài)存儲(chǔ)器)
中文描述: 2.6兆比特的動(dòng)態(tài)影視順序訪問(wèn)應(yīng)用程序的內(nèi)存(電視,SAM)的具有片上降噪過(guò)濾器(應(yīng)用于電視的260萬(wàn)位動(dòng)態(tài)存儲(chǔ)器)
文件頁(yè)數(shù): 19/32頁(yè)
文件大?。?/td> 182K
代理商: SDA 9254-2
SDA 9254-2
Semiconductor Group
19
1998-01-16
Refresh period
t
REF
16
ms
Either 256 refresh cycles or
read/write cycles on 212
consecutive row addresses
have to be performed
within the 16 ms interval to
maintain data
Transition time
(rise/fall)
t
T
2
10
ns
Transition times are
measured between
V
IH
and
V
IL
.
See diagram 1
L-serial clock time
t
SCL
t
SCH
10
ns
See diagram 2
H-serial clock time
Hold time from SCA
t
CAH
Hold time from SCB
t
CBH
Input capacitance
(SCA, SCB)
10
ns
See diagram 2
6
ns
See diagram 2
6
ns
See diagram 3, 7
f
= 1 MHz
C
I 1
7
pF
Input capacitance
(all other pins)
C
I 2
5
pF
f
= 1 MHz
Output capacitance
(SQA 0-11,
DLO 0 ... 3)
C
Q
7
pF
f
= 1 MHz
AC Characteristics
(cont’d)
V
DD
= 5 V
±
10 %;
T
A
= 0 to 70
°
C
Parameter
Symbol
Limit Values
Unit
Test Condition
min.
typ.
max.
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參數(shù)描述
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