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參數(shù)資料
| 型號： | sda 9205 |
| 廠商： | SIEMENS AG |
| 英文描述： | Triple 8-Bit Analog-to-Digital-Converter(三倍8位A/D轉(zhuǎn)換器) |
| 中文描述： | 三8位模擬到數(shù)字轉(zhuǎn)換器（三倍8位的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 5/31頁 |
| 文件大?。?/td> | 560K |
| 代理商： | SDA 9205 |
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SDA 9205-2
Semiconductor Group
5
Circuit Description
Analog to Digital Converter
The SDA 9205-2 implements 3 independent 8-bit analog-to-digital converters.
They are two step converters with a coarse comparator block and two fine comparator blocks each
using pipeline architecture for high speed sampling performance. During the first clock cycle, the
coarse comparator samples and determines 4 MSBs and one of the fine comparator blocks
samples the input voltage. During the second clock cycle this fine comparator block makes its
decision for the 4 LSBs. So the coarse comparator block makes its decisions at each clock cycle,
the fine comparator blocks make the comparison alternating every two clock cycles.
The converter uses the redundancy principle to correct fine conversion. The sample and hold
function has been distributed in each comparator due to the two step conversion principle.
Clamping
An internal clamping circuit is provided in each of three analog channels. The analog pins AINA,
AINB, AINC are switched simultaneously to on chip generated clamping levels by an active high
pulse on pin 30 (CLAMP).
Clamping Levels
Analog Channel
Dual Code
Components
AINA
00010000
(Y)
AINB, AINC
10000000
(U, V)
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相關(guān)代理商/技術(shù)參數(shù) |
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| SDA9205-2 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Triple 8-Bit Analog-to-Digital-Converter |
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