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參數(shù)資料
| 型號： | sda 9205 |
| 廠商： | SIEMENS AG |
| 英文描述： | Triple 8-Bit Analog-to-Digital-Converter(三倍8位A/D轉(zhuǎn)換器) |
| 中文描述： | 三8位模擬到數(shù)字轉(zhuǎn)換器（三倍8位的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 24/31頁 |
| 文件大?。?/td> | 560K |
| 代理商： | SDA 9205 |
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SDA 9205-2
Semiconductor Group
24
Digital Inputs
L-input voltage
H-input voltage
V
IL
V
IH
I
I
0
2.0
0.8
V
DD
10
V
V
μ
A
Input current
– 10
5
V
I
= 0 V,
V
CC
Digital Outputs
L-output voltage
H-output voltage
V
QL
V
QH
I
QZ
2.4
0.4
V
V
μ
A
I
SINK
= 1.6 mA
I
SOURCE
= 400 mA
V
Q
= 0 V,
V
CC
High impedance state
output current
– 20
20
Performance
Sampling rate
27
30
MSPS
Full power bandwidth
(– 3 dB)
BW
10
MHz
Diff. linearity (D.C.)
DNLE
±
0.5
±
1
±
3
±
3
LSB
Int. linearity (D.C.)
INLE
±
0.5
±
1
LSB
Clamping level accuracy
CLA
LSB
Gain error
GE
LSB
Differential gain
1)
DG
3
%
f
I
= 3.6/4.4 MHz
AIN = 1/10 FSR
2 )
Differential phase
1)
DP
α
S/N
3
degree
Signal-to-noise ratio
4.4 MHz sinus
42
46
dB
without harmonics
4:1:1 mode DSP 1.0
Harmonic Distorsion
2./4. order
3. order
5./6. order
– 40
– 40
– 46
dB
dB
dB
4.4 MHz fundamental
4.4 MHz fundamental
4.4 MHz fundamental
Supply voltage rejection
2.5
%FSR/V
2)
1)
Sample test
Full scale range (FSR) = 2 V as specified
2)
Characteristics
(cont’d)
V
DD
= 5 V
±
5 %,
V
CC
= 5 V
±
5 %,
V
REFH
= 2.5 V,
V
REFL
= 0.5 V,
V
GND
= 0 V
f
CLK
= 27 MHz, all specifications min (
T
A
) to max (
T
A
) unless otherwise noted
Parameter
Symbol
Limit Values
Unit
Test Condition
min.
typ.
max.
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