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參數(shù)資料
| 型號(hào)： | SDA 4335 |
| 廠商： | SIEMENS AG |
| 元件分類： | 通用總線功能 |
| 英文描述： | PLL Frequency Synthesizer, IF Counter, 7 bit ADC, 7 & 4 bit DAC(包含IF計(jì)數(shù)器,7位ADC,7和4位DAC的用于汽車收音機(jī)的鎖相環(huán)頻率合成器) |
| 中文描述： | 鎖相環(huán)頻率合成器，中頻計(jì)數(shù)器，7位ADC，7 |
| 文件頁(yè)數(shù)： | 28/33頁(yè) |
| 文件大小： | 676K |
| 代理商： | SDA 4335 |
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Specification
SDA 4335
Semiconductor Group
28
21.5.99
1)
only in I
2
C bus mode
2)
only in 3W bus mode
3)
C
b
= capacitance of one bus line in pF.
Note that the maximum t
F
for the SDA and SCL bus lines quoted at 300ns is longer than the specified maxi-
mum t
OF
for the output stages (250ns).This allows series protection resistors to be connected between the
SDA / SCL pins and the SDA /SCL bus lines without exceeding the maximum specified t
F
.
Parameter
Symbol
Limit Values
Unit
min.
max.
LOW level input voltage
(SDA, SCL, BUS_ENA, BUS_MODE)
HIGH level input voltage
(SDA, SCL, BUS_ENA, BUS_MODE)
Pulse widh of spikes which must be suppressed by the
input filter
LOW level output voltage 3mA sink current (SDA)
Output fall time from V
IHmin
to V
ILmax
with a bus capaci-
tance from 10pF to 400pFwith up to 3mA
SCL clock frequency
Bus free time between a STOP and START condition
1)
t
BUF
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
1)
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
1)
Data hold time
Data set -up time
Rise, fall time of both SDA and SCL signals
Set-up time for STOP condition
1)
Capacitive load for each bus line
Setup time SCL to BUS_ENA
2)
H-pulsewidth (BUS_ENA)
V
IL
-0.5
0.90
V
V
IH
2.10
5.50
V
t
SP
0
50
ns
V
OL
0
0.40
V
t
OF
20+0.1C
b3)
250
ns
f
SCL
0
1.3
400
kHz
us
t
HO.STA
0.6
us
t
LOW
t
HIGH
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
, t
F
t
SU.STO
C
b
t
SU.SCLEN
t
WHEN
1.3
0.6
0.6
0
100
20+0.1C
b3)
0.6
us
us
us
ns
ns
ns
us
pF
us
us
300
400
0.6
0.6
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