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參數(shù)資料
| 型號： | SDA 4335 |
| 廠商： | SIEMENS AG |
| 元件分類： | 通用總線功能 |
| 英文描述： | PLL Frequency Synthesizer, IF Counter, 7 bit ADC, 7 & 4 bit DAC(包含IF計數(shù)器,7位ADC,7和4位DAC的用于汽車收音機的鎖相環(huán)頻率合成器) |
| 中文描述： | 鎖相環(huán)頻率合成器，中頻計數(shù)器，7位ADC，7 |
| 文件頁數(shù)： | 15/33頁 |
| 文件大?。?/td> | 676K |
| 代理商： | SDA 4335 |
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Specification
SDA 4335
Semiconductor Group
15
21.5.99
I
2
C bus mode
In this mode pin7 (BUS_MODE) = low and pin10 (BUS_ENA)=low. In this mode SDA is a
bidirectional input / output pin.
Data Transition:
Data transition on the pin SDA must only occur when the clock SCL is low. SDA transitions while
SCL is high will be interpreted as start or stop condition.
Start Condition (STA):
A start condition is defined by a high to low transition of the SDA line while SCL is at a stable high
level.This start condition must precede any command and initiate a data transfer onto the bus.
Stop Condition (STO):
A stop condition is defined by a low to high transition of the SDA while the SCL line is at a stable
high level. This condition terminate the communication between the devices and forces the bus
interface into the initial conditions.
Acknowlage (ACK):
Indicates a successful data transfer. The transmitter will release the bus after sending 8 bit of data.
During the 9th clock cycle the receiver will pull the SDA line to low level to indicate it has receive the
8 bits of data correctly.
Data Transfer Write Mode:
To start the communication, the bus master must initiate a start condition, followed by the 8bit chip
address (write). The chip address for the SDA 4335 is fixed as ”1100110” (MSB at first). The last bit
(LSB=A0) of the chip address byte defines the typ of operation to be performed:
A0=1, a read operation is selected and A0=0, a write operation is selected. After this comparision
the SDA 4335 will generate an ACK.
After this device addressing the desired sub address byte and data bytes must be followed. The
subaddresses determines which one of the 9 data bytes (00H...07H, 0BH) is transmitted first. At the end
of data transition the master must be generate the stop condition.
Data Transfer Read Mode:
To start the communication in the read mode, the bus master must initiate a start condition, fol
lowed by the 8bit chip address (write: A0=0), followed by the sub address read (82H or 83H),
followed by the chip address (read: A0=1). After that procedure the 16bit data register 82H or the
8bit data register 83H is read out. After the first 8 bit read out, the uP mandatory send LOW during
the ACK-clock. After the second 8 bit read out the uP mandatory send HIGH during the ACK-clock.
At the end of data transition the master must be generate the stop condition.
3W bus mode
In this mode pin4 (BUS_MODE) =high. Pin6 (SDA) is a bidirectional input / output pin in this mode.
Pin8 (BUS_ENA) is used to activate the bus interface to allow the transfer of data to / from the
device. When BUS_ENA is in an inactive high state, shifting is inhibited.
Data Transition:
Data transition on the pin SDA must only occur when the clock SCL is low. To transfer data to / from
the device, BUS_ENA (which must start inactive high) is taken low, a serial transfer is made via
SDA, CLK and BUS_ENA is taken back high. The bit stream needs neither the chip address.
Data Transfer Write Mode:
To start the communication, the BUS_ENA is taken low. The desired sub address byte and data
bytes must be followed. The subaddresses determines which one of the 9 data bytes (00H...07H,
0BH) is transmitted first. At the end of data transition the BUS_ENA must be high.
Data Transfer Read Mode:
To start the communication in the read mode, the BUS_ENA is taken low, followed by the sub
address read (82H or 83H). After that the device is ready to read out the 16bit data register 82H or
the 8bit data register 83H. At the end of data transition the BUS_ENA must be high.
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