參數(shù)資料
型號(hào): SCAN18541TSSC
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Non-Inverting Line Driver with 3-STATE Outputs
中文描述: SCAN/JTAG/3J SERIES, DUAL 9-BIT BOUNDARY SCAN DRIVER, TRUE OUTPUT, PDSO56
封裝: 0.300 INCH, MO-118, SSOP-56
文件頁數(shù): 3/11頁
文件大?。?/td> 90K
代理商: SCAN18541TSSC
3
www.fairchildsemi.com
S
Description of Boundary-Scan Circuitry
The scan cells used in the BOUNDARY-SCAN register are
one of the following two types depending upon their loca-
tion. Scan cell TYPE1 is intended to solely observe system
data, while TYPE2 has the additional ability to control sys-
tem data.
Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is located at each system output pin as
well as at each of the two internal active-high output enable
signals. AOE controls the activity of the A-outputs while
BOE controls the activity of the B-outputs. Each will acti-
vate their respective outputs by loading a logic high.
The BYPASS register is a single bit shift register stage
identical to scan cell TYPE1. It captures a fixed logic low.
Bypass Register Scan Chain Definition
Logic 0
The INSTRUCTION register is an 8-bit register which cap-
tures the default value of 10000001. The two least signifi-
cant bits of this captured value (01) are required by IEEE
Std 1149.1. The upper six bits are unique to the
SCAN18541T device. SCAN CMOS Test Access Logic
devices do not include the IEEE 1149.1 optional identifica-
tion register. Therefore, this unique captured value can be
used as a
pseudo ID
code to confirm that the correct
device is placed in the appropriate location in the boundary
scan chain.
Instruction Register Scan Chain Definition
MSB
LSB
Scan Cell TYPE1
Scan Cell TYPE2
Instruction Code
00000000
10000001
10000010
00000011
All Others
Instruction
EXTEST
SAMPLE/PRELOAD
CLAMP
HIGH-Z
BYPASS
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