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參數(shù)資料
| 型號： | SC68C752B |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs and Motorola mP interface |
| 中文描述： | 5伏，3.3伏和2.5伏兆5雙UART /秒（最大），64字節(jié)的FIFO和摩托羅拉手機接口 |
| 文件頁數(shù)： | 30/46頁 |
| 文件大?。?/td> | 219K |
| 代理商： | SC68C752B |
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9397 750 14963
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 28 April 2005
30 of 46
Philips Semiconductors
SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Remark:
TCR can only be written to when EFR[4] = 1 and MCR[6] = 1. The programmer
must program the TCR such that TCR[3:0] > TCR[7:4]. There is no built-in hardware
check to make sure this condition is met. Also, the TCR must be programmed with this
condition before Auto-RTS or software flow control is enabled to avoid spurious operation
of the device.
7.13 Trigger Level Register (TLR)
This 8-bit register is pulsed to store the transmit and received FIFO trigger levels used for
DMA and interrupt generation. Trigger levels from 4 to 60 can be programmed with a
granularity of 4.
Table 22
shows trigger level register bit settings.
Remark:
TLR can only be written to when EFR[4] = 1 and MCR[6] = 1. If TLR[3:0] or
TLR[7:4] are logical 0, the selectable trigger levels via the FIFO control register (FCR) are
used for the transmit and receive FIFO trigger levels. Trigger levels from
4 bytes to 60 bytes are available with a granularity of four. The TLR should be
programmed for
N
4
, where N is the desired trigger level.
When the trigger level setting in TLR is zero, the SC68C752B uses the trigger level setting
defined in FCR. If TLR has non-zero trigger level value, the trigger level defined in FCR is
discarded. This applies to both transmit FIFO and receive FIFO trigger level setting.
When TLR is used for RX trigger level control, FCR[7:6] should be left at the default state,
that is, ‘00’.
7.14 FIFO ready register
The FIFO ready register provides real-time status of the transmit and receive FIFOs of
both channels.
The FIFO Rdy register is a read-only register that can be accessed when any of the two
UARTs is selected CS = 0, MCR[2] (FIFO Rdy Enable) is a logic 1, and loop-back is
disabled. The address is 111.
Table 22:
Bit
7:4
3:0
Trigger Level Register bits description
Symbol
Description
TLR[7:4]
RX FIFO trigger levels (4 to 60), number of characters available.
TLR[3:0]
TX FIFO trigger levels (4 to 60), number of spaces available.
Table 23:
Bit
7:6
5
4
3:2
1
0
FIFO ready register bits description
Symbol
FIFO Rdy[7:6]
FIFO Rdy[5]
FIFO Rdy[4]
FIFO Rdy[3:2]
FIFO Rdy[1]
FIFO Rdy[0]
Description
unused; always 0
RX FIFO B status; related to DMA
RX FIFO A status; related to DMA
unused; always 0
TX FIFO B status; related to DMA
TX FIFO A status; related to DMA
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SC68C752BIB48 | 功能描述:UART 接口集成電路 2.5V-5V 2CH UART 64B FIFO MOT RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC68C752BIB48,128 | 功能描述:UART 接口集成電路 2.5V-5V 2CH UART 64B RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC68C752BIB48,151 | 功能描述:UART 接口集成電路 UART DUAL W/FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC68C752BIB48,157 | 功能描述:UART 接口集成電路 2.5V-5V 2CH UART 64B RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC68C752BIB48-F | 功能描述:UART 接口集成電路 2.5V-5V 2CH UART 64B FIFO MOT RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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