參數(shù)資料
型號(hào): SC68C752B
廠商: NXP Semiconductors N.V.
英文描述: 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs and Motorola mP interface
中文描述: 5伏,3.3伏和2.5伏兆5雙UART /秒(最大),64字節(jié)的FIFO和摩托羅拉手機(jī)接口
文件頁數(shù): 29/46頁
文件大?。?/td> 219K
代理商: SC68C752B
9397 750 14963
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 28 April 2005
29 of 46
Philips Semiconductors
SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
7.10 Enhanced Feature Register (EFR)
This 8-bit register enables or disables the enhanced features of the UART.
Table 20
shows
the enhanced feature register bit settings.
7.11 Divisor latches (DLL, DLH)
These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock
in the baud rate generator. DLH stores the most significant part of the divisor. DLL stores
the least significant part of the divisor.
Note that DLL and DLH can only be written to before Sleep mode is enabled, that is,
before IER[4] is set.
7.12 Transmission Control Register (TCR)
This 8-bit register is used to store the RX FIFO threshold levels to stop/start transmission
during hardware/software flow control.
Table 21
shows transmission control register bit
settings.
TCR trigger levels are available from 0 bytes to 60 bytes with a granularity of four.
Table 20:
Bit
7
Enhanced Feature Register bits description
Symbol
Description
EFR[7]
CTS flow control enable.
logic 0 = CTS flow control is disabled (normal default condition)
logic 1 = CTS flow control is enabled. Transmission will stop when a HIGH
signal is detected on the CTS pin.
EFR[6]
RTS flow control enable.
logic 0 = RTS flow control is disabled (normal default condition)
logic 1 = RTS flow control is enabled. The RTS pin goes HIGH when the
receiver FIFO HALT trigger level TCR[3:0] is reached, and goes LOW when
the receiver FIFO RESUME transmission trigger level TCR[7:4] is reached.
EFR[5]
Special character detect.
logic 0 = special character detect disabled (normal default condition)
logic 1 = special character detect enabled. Received data is compared with
Xoff-2 data. If a match occurs, the received data is transferred to FIFO and
IIR[4] is set to a logical 1 to indicate a special character has been detected.
EFR[4]
Enhanced functions enable bit.
logic 0 = disables enhanced functions and writing to IER[7:4], FCR[5:4],
MCR[7:5]
logic 1 = enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5]
can be modified, that is, this bit is therefore a write enable
EFR[3:0]
Combinations of software flow control can be selected by programming these
bits. See
Table 4 “Software flow control options (EFR[0:3])” on page 9
.
6
5
4
3:0
Table 21:
Bit
7:4
3:0
Transmission Control Register bits description
Symbol
Description
TCR[7:4]
RX FIFO trigger level to
resume
transmission (0 bytes to 60 bytes).
TCR[3:0]
RX FIFO trigger level to
halt
transmission (0 bytes to 60 bytes).
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SC68C752BIB48,128 功能描述:UART 接口集成電路 2.5V-5V 2CH UART 64B RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC68C752BIB48,151 功能描述:UART 接口集成電路 UART DUAL W/FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC68C752BIB48,157 功能描述:UART 接口集成電路 2.5V-5V 2CH UART 64B RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC68C752BIB48-F 功能描述:UART 接口集成電路 2.5V-5V 2CH UART 64B FIFO MOT RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel