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參數(shù)資料
| 型號： | SC16C852VIET,151 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 4/55頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART DUAL W/FIFO 36TFBGA |
| 標準包裝： | 490 |
| 特點： | 可編程 |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 128 字節(jié) |
| 規(guī)程： | RS485 |
| 電源電壓： | 2.5V |
| 帶自動流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調制解調器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-TFBGA |
| 供應商設備封裝： | 36-TFBGA（3.5x3.5） |
| 包裝： | 托盤 |
| 其它名稱： | 568-5662 935282518151 SC16C852VIET,151-ND SC16C852VIET-S SC16C852VIET-S-ND |
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SC16C852V
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 21 January 2011
12 of 55
NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
When AFCR1[2] is set to 1, then the function of CTSx pin is mapped to the DSRx pin, and
the function of RTS is mapped to DTRx pin. DSRx and DTRx pins will behave as
described above for CTSx and RTSx.
With the automatic hardware flow control function enabled, an interrupt is generated when
the receive FIFO reaches the programmed trigger level. The RTSx (or DTRx) pin will not
be forced to a logic 1 (RTS off) until the receive FIFO reaches the next trigger level.
However, the RTSx (or DTRx) pin will return to a logic 0 after the receive buffer (FIFO) is
unloaded to the next trigger level below the programmed trigger level. Under the above
described conditions, the SC16C852V will continue to accept data until the receive FIFO
is full.
When TXINTLVL, RXINTLVL, FLWCNTH and FLWCNTL in the First Extra Register Set
are all zeroes, the hardware and software flow control trigger levels are set by FCR[7:4];
see Table 5.
When either TXINTLVL, RXINTLVL, FLWCNTH or FLWCNTL in the First Extra Register
Set contains any value other than 0x00, the hardware and software flow control trigger
levels are set by FLWCNTH and FLWCNTL. The content in FLWCNTH determines how
many bytes are in the receive FIFO before RTSx (or DTRx) is de-asserted or XOFF is
sent. The content of FLWCNTL determines how many bytes are in the receive FIFO
before RTSx (or DTRx) is asserted, or XON is sent.
In 128-byte FIFO mode, hardware and software flow control trigger levels can be set to
any value between 1 and 128 in granularity of 1. The value of FLWCNTH should always
be greater than FLWCNTL. The UART does not check for this condition automatically, and
if this condition is not met spurious operation of the device might occur. When using
FLWCNTH and FWLCNTL, these registers must be initialized to the proper values before
hardware or software flow control is enabled via the EFR register.
6.6 Software flow control
When software flow control is enabled, the SC16C852V compares one or two sequentially
received data characters with the programmed Xon or Xoff character value(s). If the
received character(s) match the programmed Xoff values, the SC16C852V will halt
transmission (TX) as soon as the current character(s) has completed transmission. When
a match occurs, ISR bit 4 will be set (if enabled via IER[5]) and the interrupt output pin (if
receive interrupt is enabled) will be activated. Following a suspension due to a match of
the Xoff characters’ values, the SC16C852V will monitor the receive data stream for a
match to the Xon1/Xon2 character value(s). If a match is found, the SC16C852V will
resume operation and clear the flags (ISR[4]).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0.
Following reset, the user can write any Xon/Xoff value desired for software flow control.
Different conditions can be set to detect Xon/Xoff characters and suspend/resume
transmissions (see Table 26). When double 8-bit Xon/Xoff characters are selected, the
SC16C852V compares two consecutive receive characters with two software flow control
8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under
the above described flow control mechanisms, flow control characters are not placed
(stacked) in the receive FIFO. When using software flow control, the Xon/Xoff characters
cannot be used for data transfer.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SC16C852VIET-G | 功能描述:UART 接口集成電路 1.8V 2CH UART 128B FIFO 5MBPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C852VIET-S | 功能描述:UART 接口集成電路 1.8V 2CH UART 128B FIFO 5MBPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16DP-26 | 制造商:Thomas & Betts 功能描述:SAXXIT CABLE CLIP W/ DRIVE PIN -7 制造商:Belden Inc 功能描述: |
| SC16DP-3Q | 制造商:Thomas & Betts 功能描述:SAXXIT CABLE CLIP W/ DRIVE PIN -8 |
| SC16-FM-M16-NPB-ML-1 | 制造商:HellermannTyton 功能描述: |
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