參數(shù)資料
型號: SC16C852VIET,151
廠商: NXP Semiconductors
文件頁數(shù): 28/55頁
文件大?。?/td> 0K
描述: IC UART DUAL W/FIFO 36TFBGA
標準包裝: 490
特點: 可編程
通道數(shù): 2,DUART
FIFO's: 128 字節(jié)
規(guī)程: RS485
電源電壓: 2.5V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 36-TFBGA
供應商設備封裝: 36-TFBGA(3.5x3.5)
包裝: 托盤
其它名稱: 568-5662
935282518151
SC16C852VIET,151-ND
SC16C852VIET-S
SC16C852VIET-S-ND
SC16C852V
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 21 January 2011
34 of 55
NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
[1]
When using a software flow control the Xon/Xoff characters cannot be used for data transfer.
7.15 Transmit Interrupt Level register (TXINTLVL)
This 8-bit register is used store the transmit FIFO trigger levels used for DMA and
interrupt generation. Trigger levels from 1 to 128 can be programmed with a granularity
of 1. Table 27 shows trigger level register bit settings.
[1]
For 32-byte FIFO mode, refer to Section 7.3 “FIFO Control Register (FCR)”.
7.16 Receive Interrupt Level register (RXINTLVL)
This 8-bit register is used store the receive FIFO trigger levels used for DMA and interrupt
generation. Trigger levels from 1 to 128 can be programmed with a granularity of 1.
Table 28 shows trigger level register bit settings.
[1]
For 32-byte FIFO mode, refer to Section 7.3 “FIFO Control Register (FCR)”.
1
X
Transmit Xon1 and Xon2/Xoff1 and Xoff2
X
0
No receive flow control
X
1
0
Receiver compares Xon1/Xoff1
X
0
1
Receiver compares Xon2/Xoff2
1
0
1
Transmit Xon1/Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0
1
Transmit Xon2/Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1
Transmit Xon1 and Xon2, Xoff1 and Xoff2
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
Table 26.
Software flow control functions[1] …continued
Cont-3
Cont-2
Cont-1
Cont-0
TX, RX software flow controls
Table 27.
TXINTLVL register bits description
Bit
Symbol
Description
7:0
TXINTLVL[7:0]
This register stores the programmable transmit interrupt trigger levels for
128-byte FIFO mode.[1]
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
Table 28.
RXINTLVL register bits description
Bit
Symbol
Description
7:0
RXINTLVL[7:0]
This register stores the programmable receive interrupt trigger levels for
128-byte FIFO mode.[1]
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
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