參數(shù)資料
型號(hào): SAK-C167SR-LM
廠商: SIEMENS A G
元件分類: 微控制器/微處理器
英文描述: 16-Bit CMOS Single-Chip Microcontroller
中文描述: MICROCONTROLLER, MQFP144
文件頁(yè)數(shù): 68/80頁(yè)
文件大?。?/td> 1151K
代理商: SAK-C167SR-LM
C167CS-4R
C167CS-L
Data Sheet
64
V2.0, 2000-06
Table 16
Parameter
External Bus Cycle Timing
(Operating Conditions apply)
Symbol
Limits
Unit
min.
max.
15
Output delay from CLKOUT falling edge
Valid for: address (MUX on PORT0), write data out
Output delay from CLKOUT edge
Valid for: latched CS, ALE (normal)
Output delay from CLKOUT edge
Valid for: WR, WRL, WRH, WrCS
Output delay from CLKOUT edge
Valid for: RD, RdCS
Input setup time to CLKOUT falling edge
Valid for: read data in
Input hold time after CLKOUT falling edge
Valid for: read data in
1)
Output delay from CLKOUT falling edge
Valid for: address (on PORT1 and/or P4), BHE
Output hold time after CLKOUT falling edge
Valid for: address, BHE
2)
Output hold time after CLKOUT edge
3)
Valid for: write data out
Output delay from CLKOUT falling edge
Valid for: ALE (extended), early CS
Turn off delay after CLKOUT edge
3)
Valid for: write data out
Turn on delay after CLKOUT falling edge
3)
Valid for: write data out
Output hold time after CLKOUT edge
Valid for: early CS
tc
10
CC 1
ns
tc
11
CC
– 3
6
ns
tc
12
CC – 3
7
ns
tc
13
CC – 1
7
ns
tc
14
SR 12
ns
tc
15
SR – 1
ns
tc
16
CC 1
12
ns
tc
17
CC – 1
10
ns
tc
18
CC 0
ns
tc
19
CC – 5
7
ns
tc
20
CC –
7
ns
tc
21
CC – 5
ns
tc
22
CC – 6
4
ns
1)
Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge
of RD. Therefore address changes before the end of RD have no impact on (demultiplexed) read cycles.
2)
Due to comparable propagation delays the address does not change before WR goes high. The minimum
output delay (
tc
17min
) is therefore the actual value of
tc
12
.
3)
Not 100% tested, guaranteed by design and characterization.
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