參數(shù)資料
型號: SAK-C167SR-LM
廠商: SIEMENS A G
元件分類: 微控制器/微處理器
英文描述: 16-Bit CMOS Single-Chip Microcontroller
中文描述: MICROCONTROLLER, MQFP144
文件頁數(shù): 67/80頁
文件大?。?/td> 1151K
代理商: SAK-C167SR-LM
C167CS-4R
C167CS-L
Data Sheet
63
V2.0, 2000-06
AC Characteristics
Figure 16
CLKOUT Signal Timing
Variable Memory Cycles
The bus timing shown below is programmable via the BUSCONx registers. The duration
of ALE and two types of waitstates can be selected. This table summarizes the possible
bus cycle durations.
Table 14
Parameter
CLKOUT Reference Signal
Symbol
Limits
Unit
min.
max.
CLKOUT cycle time
CLKOUT high time
CLKOUT low time
CLKOUT rise time
CLKOUT fall time
tc
5
tc
6
tc
7
tc
8
tc
9
CC
CC 8
CC 6
CC –
CC –
30
1)
1)
The CLKOUT cycle time is influenced by the PLL jitter.
For a single CLKOUT cycle (2 TCL) the deviation caused by the PLL jitter is below 1 ns (for
f
CPU
> 25 MHz).
For longer periods the relative deviation decreases (see PLL deviation formula).
ns
ns
ns
ns
ns
4
4
Table 15
Bus Cycle Type
Demultiplexed bus cycle
with normal ALE
Demultiplexed bus cycle
with extended ALE
Multiplexed bus cycle with
normal ALE
Multiplexed bus cycle with
extended ALE
Variable Memory Cycles
Bus Cycle Duration
4 + 2
×
(15 – <MCTC>)
+ 2
×
(1 – <MTTC>)
6 + 2
×
(15 – <MCTC>)
+ 2
×
(1 – <MTTC>)
6 + 2
×
(15 – <MCTC>)
+ 2
×
(1 – <MTTC>)
8 + 2
×
(15 – <MCTC>)
+ 2
×
(1 – <MTTC>)
Unit 25/33 MHz, 0 Waitstates
TCL 80 ns
/ 60.6 ns
TCL 120 ns / 90.9 ns
TCL 120 ns / 90.9 ns
TCL 160 ns / 121.2 ns
MCT04415
CLKOUT
tc
5
tc
6
7
tc
8
tc
9
tc
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相關代理商/技術參數(shù)
參數(shù)描述
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SAK-C167SR-LM HA+ TR 制造商:Infineon Technologies AG 功能描述:
SAK-C167SR-LMHA+ 制造商:Infineon Technologies AG 功能描述: 制造商:Rochester Electronics LLC 功能描述:
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