
C165UTAH
External Bus Interface
Data Sheet
178
2001-02-23
Single Chip Mode
Single chip mode is entered, when pin EA is high during reset. In this case register
BUSCON0 is initialized with 0000
H
, which also resets bit BUSACT0, so no external bus
is enabled.
In single chip mode the C165UTAH operates only with and out of internal resources. No
external bus is configured and no external peripherals and/or memory can be accessed.
Also no port lines are occupied for the bus interface. When running in single chip mode,
however, external access may be enabled by configuring an external bus under software
control.
Note:
Any attempt to access a location in the external memory space in single chip mode
results in the hardware trap ILLBUS.
10.1
External Bus Modes
When the external bus interface is enabled (bit BUSACTx=’1’) and configured (bitfield
BTYP), the C165UTAH uses a subset of its port lines together with some control lines to
build the external bus.
The bus configuration (BTYP) for the address windows (BUSCON4...BUSCON1) is
selected via software typically during the initialization of the system.
The bus configuration (BTYP) for the default address range (BUSCON0) is selected via
PORT0 during reset, provided that pin EA is low during reset. Otherwise BUSCON0 may
be programmed via software just like the other BUSCON registers.
The 16 MByte address space of the C165UTAH is divided into 256 segments of 64 KByte
each. The 16-bit intra-segment address is output on PORT0 for multiplexed bus modes
or on PORT1 for demultiplexed bus modes. When segmentation is disabled, only one 64
KByte segment can be used and accessed. Otherwise additional address lines may be
output on Port 4, and/or several chip select lines may be used to select different memory
banks or peripherals. These functions are selected during reset via bitfields SALSEL and
CSSEL of register RP0H, respectively.
Note:
Bit SGTDIS of register SYSCON defines, if the CSP register is saved during
interrupt entry (segmentation active) or not (segmentation disabled).
BTYP Encoding External Data Bus Width
External Address Bus Mode
0 0
8-bit Data
Demultiplexed Addresses
0 1
8-bit Data
Multiplexed Addresses
1 0
16-bit Data
Demultiplexed Addresses
1 1
16-bit Data
Multiplexed Addresses