參數(shù)資料
型號： SAF82525N
廠商： INFINEON TECHNOLOGIES AG
英文描述： Data Communications ICs
中文描述： 數(shù)據(jù)通信集成電路
文件頁數(shù)： 71/126頁
文件大?。?/td> 730K
代理商： SAF82525N
Semiconductor Group
71
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Table 9
User Demand Registers
User Demand
Register
CTS/RFS Interrupt Provided
CCR2
Selective Interrupts Should be Masked
MASK
Timer will be used by CPU (external timer mode)
TIMR
DMA Controlled Data Transfer
XBCH
Receive Length Check Feature
RLCR
Extended (module 128) Counting
RAH2
7.3 Operational Phase
After having performed the initialization, the CPU switches each individual channel of the
HSCX into operational phase by setting the PU bit in the CCR1 register (power-up, if not
already done during initialization).
Initially, the CPU should bring the transmitter and receiver to a defined state by issuing a XRES
(transmitter reset) and RHR (receiver reset) command via the CMDR register. If data reception
should be performed, the receiver must be activated by setting the RAC bit in MODE to 1.
If no "Clear to send" function is provided via a modem, the CTS pin of the HSCX must be
connected directly to ground, in order to enable data transmission.
Now the HSCX is ready to transmit and receive data. The control of the data transfer phase is
mainly done by commands from CPU to HSCX via the CMDR register, and by interrupt
indications from HSCX to CPU.
Additional status information, which does not trigger an interrupt, is available in the STAR
register.
7.4 Data Transmission
Interrupt Mode
In transmit direction 2
×
32 byte FIFO buffers (transmit pools) are provided for each channel.
After checking the XFIFO status by polling the Transmit FIFO Write Enable bit (XFW in STAR
register) or after a Transmit Pool Ready (XPR) interrupt, up to 32 bytes may be entered by the
CPU to the XFIFO.
The transmission of a frame can then be started issuing a XTF or XIF command via the CMDR
register. If the transmit command does not include an end of message indication
(CMDR : XME), the HSCX will repeatedly request for the next data block by means of a XPR
interrupt as soon as no more than 32 bytes are stored in the XFIFO, i.e. a 32-byte pool is
accessible to the CPU.
This process will be repeated until the CPU indicates the end of message per command, after
which frame transmission is finished correctly by appending the CRC and closing flag
sequence.
In case no more data is available in the XFIFO prior to the arrival of XME, the transmission of
the frame is terminated with an abort sequence and the CPU is notified per interrupt
(EXIR : XDU). The frame may also be aborted per software (CMDR : XRES).
The data transmission sequence, from the CPU’s point of view, is outlined in
figure 32.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAF82525NV2.1 制造商:Infineon Technologies AG 功能描述:
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SAF82525NV21 制造商:Infineon Technologies AG 功能描述:Communication Controller 44-Pin PLCC
SAF82525N-V21 功能描述:IC CONTROLLER 2-CH SER 44-PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
SAF82525V2.1 制造商:Rochester Electronics LLC 功能描述:- Bulk
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