參數(shù)資料
型號: SAF82525N
廠商: INFINEON TECHNOLOGIES AG
英文描述: Data Communications ICs
中文描述: 數(shù)據(jù)通信集成電路
文件頁數(shù): 59/126頁
文件大?。?/td> 730K
代理商: SAF82525N
Semiconductor Group
59
SAB 82525
SAB 82526
SAF 82525
SAF 82526
– Phase Shift
In the case the DPLL detects an edge in the data stream in the range of DPLL count 5 to 10
(Phase Shift) and this is the only one in the assumed bit cell period, then the DPLL receive
clock phase is shifted by a certain DPLL count value.
Figure 28d
Synchronization of the Data Clock in DPLL Mode: Interference Rejection and Phase
Adjustment
The DPLL value and its corresponding phase shift in degree is listed below for the HSCX
versions VA3 and V2.1:
Note:
The operating characteristics of the DPLL therefore allow a phase jitter of 18.75% of the
frequency.
HSCX Version
DPLL Count
Phase Shift
VA3
8
180
o
V2.1
7
157,5
o
ITD05884
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Phase Adjust
Phase Shift
+
-
Assumed Bit Cell
DPLL Input
Receive Data
DPLL Count
DPLL
Phase Correction
DPLL Output
Receive Clock
+
+
1
7
1
-
Phase Adjust
Phase Shift
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參數(shù)描述
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