參數(shù)資料
型號: SAF82525N
廠商: INFINEON TECHNOLOGIES AG
英文描述: Data Communications ICs
中文描述: 數(shù)據(jù)通信集成電路
文件頁數(shù): 44/126頁
文件大?。?/td> 730K
代理商: SAF82525N
Semiconductor Group
44
SAB 82525
SAB 82526
SAF 82525
SAF 82526
HSCX supports target synchronous as well as source synchronous DMA transfer. In source
synchronous DMA transfer mode a DMA cycle is started when an active level occurs an the
DMA request line. This request is controlled by the source (transfer peripheral device
memory).
First of all the data is read out of the peripheral device. During the second clock cycle it is writ-
ten into the memory according to the target address.
If there is target synchronous DMA transfer the DMA cycle is started when there is an active
level on the DMA request line. The request is controlled by the target (transfer memory
peripheral).
First of all the data is read from the memory. During the second clock cycle it is written into the
peripheral IC. The DMA request line continues being activated until it is reset by a write cycle
to a peripheral device IC.
ITD02697
T1
T2
T3
T4
T1
T2
T3
T4
t
DRHSYS
t
CLRL
t
INVCL
CLOCKOUT
DRQ
RD
(FIFO)
WR
(Memory)
f
CLKOUT
t
CLCL
t
CLRL
t
INVCL
t
DRHSYS
max
8 MHz
12.5
MHz
16
125 ns
ns
80
62.5
44 ns
37
31
15 ns
15
15
316 ns
188
141.5
ns
ns
ns
ns
ns
MHz
ns
ns
INVCL
t
t
CLCL
- t
CLRL
x
3
=
INVCL
t
CLRL
t
T4
+
T3
=
max
DRHSYS
t
+
T2
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參數(shù)描述
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