參數(shù)資料
型號: SAF7118
廠商: NXP Semiconductors N.V.
英文描述: Multistandard video decoder with adaptive comb filter and component video input
中文描述: 多標(biāo)準(zhǔn)視頻解碼器與自適應(yīng)梳狀濾波器和分量視頻輸入
文件頁數(shù): 159/173頁
文件大小: 950K
代理商: SAF7118
2004 Jul 22
159
Philips Semiconductors
Product speci
fi
cation
Multistandard video decoder with adaptive
comb
fi
lter and component video input
SAF7118
16 PROGRAMMING START SET-UP
16.1
Decoder part
The given values force the following behaviour of the SAF7118 decoder part:
The analog input AI11 expects an NTSC M, PAL B, D, G, H and I or SECAM signal in CVBS format; analog anti-alias
filter and AGC active
Automatic field detection enabled
Standard ITU 656 output format enabled on expansion (X) port
Contrast, brightness and saturation control in accordance with ITU standards
Adaptive comb filter for luminance and chrominance activated
Pins LLC, LLC2, XTOUT, RTS0, RTS1 and RTCO are set to 3-state.
Table 140
Decoder part start set-up values for the three main standards
SUB
ADDRESS
(HEX)
REGISTER
FUNCTION
BIT NAME
(1)
VALUES (HEX)
NTSC M
PAL B, D,
G, H AND I
SECAM
00
01
chip version
increment delay
ID7 to ID4
X, WPOFF, GUDL1, GUDL0 and
IDEL3 to IDEL0
FUSE1, FUSE0 and MODE5 to MODE0
X, HLNRS, VBSL, CPOFF, HOLDG,
GAFIX, GAI28 and GAI18
GAI17 to GAI10
GAI27 to GAI20
HSB7 to HSB0
HSS7 to HSS0
AUFD, FSEL, FOET, HTC1, HTC0,
HPLL, VNOI1 and VNOI0
BYPS, YCOMB, LDEL, LUBW and
LUFI3 to LUFI0
DBRI7 to DBRI0
read only
47
47
47
02
03
analog input control 1
analog input control 2
C0
10
C0
10
C0
10
04
05
06
07
08
analog input control 3
analog input control 4
horizontal sync start
horizontal sync stop
sync control
90
90
EB
E0
98
90
90
EB
E0
98
90
90
EB
E0
98
09
luminance control
40
40
1B
0A
luminance brightness
control
luminance contrast
control
chrominance saturation
control
chrominance hue control
chrominance control 1
80
80
80
0B
DCON7 to DCON0
44
44
44
0C
DSAT7 to DSAT0
40
40
40
0D
0E
HUEC7 to HUEC0
CDTO, CSTD2 to CSTD0, DCVF, FCTC,
AUTO0 and CCOMB
ACGC and CGAIN6 to CGAIN0
OFFU1, OFFU0, OFFV1, OFFV0,
CHBW and LCBW2 to LCBW0
COLO, RTP1, HDEL1, HDEL0, RTP0
and YDEL2 to YDEL0
00
89
00
81
00
D0
0F
10
chrominance gain control
chrominance control 2
2A
0E
2A
06
80
00
11
mode/delay control
00
00
00
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