
2004 Jul 22
11
Philips Semiconductors
Product speci
fi
cation
Multistandard video decoder with adaptive
comb
fi
lter and component video input
SAF7118
Notes
1.
2.
I = input, O = output, P = power, NC = not connected, st = strapping, pu = pull-up, pd = pull-down, od = open-drain.
In accordance with the
“IEEE1149.1”
standard the pads TDI, TMS, TCK and TRST are input pads with an internal
pull-up transistor and TDO is a 3-state output pad.
For board design without boundary scan implementation connect the TRST pin to ground.
This pin provides easy initialization of the Boundary Scan Test (BST) circuit. TRST can be used to force the Test
Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once.
Pin strapping is done by connecting the pin to the supply via a 3.3 k
resistor. During the power-up reset sequence
the corresponding pins are switched to input mode to read the strapping level. For the default setting no strapping
resistor is necessary (internal pull-down).
3.
4.
5.
XPD3
XPD2
V
DDD11
V
SSD11
XPD1
XPD0
XRV
XRH
V
DDD12
XCLK
XDQ
V
SSD12
XRDY
TRST
134
135
136
137
138
139
140
141
142
143
144
145
146
147
B9
A9
C9
D9
B8
A8
D8
C7
C8
A7
B7
D7
A6
C6
I/O
I/O
P
P
I/O
I/O
I/O
I/O
P
I/O
I/O
P
O
I/pu
MSB
4 of expansion port data
MSB
5 of expansion port data
digital supply voltage 11 (peripheral cells)
digital ground 11 (peripheral cells)
MSB
6 of expansion port data
LSB of expansion port data
vertical reference I/O expansion port
horizontal reference I/O expansion port
digital supply voltage 12 (core)
clock I/O expansion port
data quali
fi
er for expansion port
digital ground 12 (core)
task
fl
ag or ready signal from scaler, controlled by XRQT
test reset input (active LOW), for boundary scan test (with internal
pull-up); notes 2, 3 and 4
test clock for boundary scan test; note 2
test mode select input for boundary scan test or scan test; note 2
test data output for boundary scan test; note 2
digital supply voltage 13 (peripheral cells)
test data input for boundary scan test; note 2
digital ground 13 (peripheral cells)
ground for crystal oscillator
input terminal for 24.576 MHz (32.11 MHz) crystal oscillator or connection
of external oscillator with TTL compatible square wave clock signal
24.576 MHz (32.11 MHz) crystal oscillator output; not connected if TTL
clock input of XTALI is used
supply voltage for crystal oscillator
crystal oscillator output signal; auxiliary signal
do not connect, reserved for future extensions and for testing
do not connect, reserved for future extensions and for testing
TCK
TMS
TDO
V
DDD13
TDI
V
SSD13
V
SS(xtal)
XTALI
148
149
150
151
152
153
154
155
B6
D6
A5
C5
B5
D5
A4
B4
I/pu
I/pu
O
P
I/pu
P
P
I
XTALO
156
A3
O
V
DD(xtal)
XTOUT
DNC9
DNC10
157
158
159
160
B3
A2
C3
C4
P
O
NC
NC
SYMBOL
PIN
TYPE
(1)
DESCRIPTION
QFP160 HBGA156