參數(shù)資料
型號： SAB83C517A-N18-T4
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 18 MHz, MICROCONTROLLER, PQCC84
封裝： PLASTIC, LCC-84
文件頁數(shù)： 57/137頁
文件大?。?/td> 2089K
代理商： SAB83C517A-N18-T4
Semiconductor Group
4 - 1
4
System Reset
4.1
Additional Hardware Power Down Mode in the SAB 80C517A
The SAB 80C517A has an additional Power Down Mode which can be initiated by an external signal
at a dedicated pin. This pin is labeled HWPD and is a floating input line (active low). This pin
substitutes one of the VSS pins of the base types SAB 80C517 (PLCC84: Pin60; P-MQFP-100-2:
Pin36). Because this new power down mode is activated by an external hardware signal this mode
is referred to as Hardware Power Down Mode in opposite to the program controlled Software Power
Down Mode.
For a correct function of the Hardware Power Down Mode the oscillator watchdog unit including its
internal RC oscillator is needed. Therefore this unit must be enabled by pin OWE (OWE = High), if
the Hardware Power Down Mode shall be used. However, the control pin PE/SWD has no control
function for the Hardware Power Down Mode; it enables and disables only the use of all software
controlled power saving modes (Slow Down Mode, Idle Mode, Software Power Down Mode).
The function of the new Hardware Power Down Mode is as follows:
The pin HWPD controls this mode. If it is on logic high level (inactive) the part is running in the
normal operating modes. If pin HWPD gets active (low level) the part enters the Hardware Power
Down Mode; as mentioned above this is independent of the state of pin PE/SWD.
HWPD is sampled once per machine cycle. If it is found active, the device starts a complete internal
reset sequence. This takes two machine cycles; all pins have their default reset states during this
time. This reset has exactly the same effects as a hardware reset; i.e.especially the watchdog timer
is stopped and its status flag WDTS is cleared. In this phase the power consumption is not yet
reduced. After completion of the internal reset both oscillators of the chip are disabled, the on-chip
oscillator as well as the oscillator watchdog’s RC oscillator. At the same time the port pins and
several control lines enter a floating state as shown in table 4-1. In this state the power consumption
is reduced to the power down current IPD. Also the supply voltage can be reduced.
Table 4-1 also lists the voltages which may be applied at the pins during Hardware Power Down
Mode without affecting the low power consumption.
System Reset
相關(guān)PDF資料
PDF描述
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SAB83C517A-5S18-T4 8-BIT, MROM, 18 MHz, MICROCONTROLLER, PQFP100
SAB80C517A-S18-T3 8-BIT, 18 MHz, MICROCONTROLLER, PQFP100
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