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參數(shù)資料
| 型號： | SAB83C517A-N18-T4 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 18 MHz, MICROCONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 109/137頁 |
| 文件大?。?/td> | 2089K |
| 代理商： | SAB83C517A-N18-T4 |
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Device Specification
Semiconductor Group
7-11
PSEN
49
22
O
The Program Store Enable
output is a control signal that enables the
external program memory to the bus during
external fetch operations. It is activated
every six oscillator periodes except during
external data memory accesses. Remains
high during internal program execution.
ALE
50
23
O
The Address Latch Enable
output is used for latching the address into
external memory during normal operation.
It is activated every six oscillator periodes
except during an external data memory
access
EA
51
24
I
External Access Enable
When held at high level, instructions are
fetched from the internal ROM (SAB
83C517A-5 only) when the PC is less than
8000H. When held at low level, the SAB
80C517A fetches all instructions from ex-
ternal program memory. For the SAB
80C517A this pin must be tied low
P0.0 - P0.7 52 - 59
26 - 27,
30 - 35
I/O
Port 0
is an 8-bit open-drain bidirectional I/O port.
Port 0 pins that have 1 s written to them
float, and in that state can be used as high-
impe-dance inputs. Port 0 is also the
multiplexed low-order address and data
bus during accesses to external program or
data memory. In this application it uses
strong internal pull-up resistors when
issuing 1 s. Port 0 also out-puts the code
bytes during program verification in the
SAB 83C517A if ROM-Protection was not
enabled. External pull-up resistors are
required during program verification.
* I = Input
O = Output
Pin Definitions and Functions (cont’d)
Symbol
Pin Number
I/O *) Function
P-LCC-84
P-MQFP-100-2
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| SAB80C517A-S18-T3 | 8-BIT, 18 MHz, MICROCONTROLLER, PQFP100 |
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