參數資料
型號: SAB83C517A-N18-T4
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 18 MHz, MICROCONTROLLER, PQCC84
封裝: PLASTIC, LCC-84
文件頁數: 54/137頁
文件大?。?/td> 2089K
代理商: SAB83C517A-N18-T4
Semiconductor Group
3 - 15
Memory Organization
3.4.2 Control of XRAM in the SAB 80C517A
There are two control bits in register SYSCON which control the use and the bus operation during
accesses to the additional On-Chip RAM in XDATA range (
XRAM).
Special Function Register SYSCON
Reset value of SYSCON is XXXX XX01B.
The control bit XMAP0 is a global enable/disable bit for the additional On-Chip RAM (XRAM). If this
bit is set, the XRAM is disabled, all MOVX accesses use external memory via the external bus. In
this case the SAB80C517A can’t use the additional On-Chip RAM and is compatible with the types
without XRAM.
Bit
Function
XMAP0
Global enable/disable bit for XRAM memory.
XMAP0 = 0: The access to XRAM (= On-Chip XDATA memory) is enabled.
XMAP0 = 1: The access to XRAM is disabled. All MOVX accesses are performed by
the external bus.
XMAP1
Control bit for RD/WR signals during accesses to XRAM; this bit has no effect if
XRAM is disabled (XMAP0 = 1) or if addresses outside the XRAM address range are
used for MOVX accesses.
XMAP1 = 0: The signals RD and WR are not activated during accesses to XRAM.
XMAP1 = 1: The signals RD and WR are activated during accesses to XRAM.
^
=
76
5432
10
MSB
LSB
Bit No.
SYSCON
Addr. 0B1H
––
––––
XMAP1 XMAP0
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