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參數(shù)資料
| 型號(hào)： | SAB-C505-LM |
| 廠商： | SIEMENS A G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-Bit CMOS Microcontroller |
| 中文描述： | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, MQFP-44 |
| 文件頁數(shù)： | 53/85頁 |
| 文件大?。?/td> | 487K |
| 代理商： | SAB-C505-LM |
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C505L
Data Sheet
51
06.99
Table 10
Power Saving Modes Overview
Mode
Entering
Sequence
Example
ORL PCON, #01H
ORL PCON, #20H
Leaving by
Remarks
Idle mode
Occurrence of an
interrupt from a
peripheral unit
Hardware Reset
CPU clock is stopped;
CPU maintains their data;
peripheral units are active
(if enabled) and provided
with clock
Internal clock rate is reduced
to 1/32 of its nominal
frequency
CPU clock is stopped;
CPU maintains their data;
peripheral units are active
(if enabled) and provided with
1/32 of its nominal frequency
Oscillator is stopped;
contents of on-chip RAM,
XRAM and SFR’s are
maintained;
Slow Down Mode
In normal mode:
ORL PCON, #10H
ANL PCON,#0EFH
Hardware Reset
With idle mode:
ORL PCON, #01H
ORL PCON, #30H
Occurrence of an
interrupt from a
peripheral unit
Hardware reset
Software
Power Down Mode1
...
bit LCEN (LCON
register) is cleared;
bit RTPD (RTCON
register) is set;
ORL PCON, #02H
ORL PCON, #40H
...
bits LCEN and
CSEL (LCON
register) are set,
bit RTPD (RTCON
register) is cleared;
...
ORL PCON, #02H
ORL PCON, #40H
...
bit LCEN (LCON
register) is cleared;
bit RTPD (RTCON
register) is cleared;
...
ORL PCON, #02H
ORL PCON, #40H
Short low pulse at
pin P3.2/INT0
Hardware Reset
Software
Power Down Mode 2
Short low pulse at
pin P3.2/INT0 or
real-time clock
wake-up interrupt
Hardware Reset
Oscillator is stopped;
contents of on-chip RAM,
XRAM and SFR’s are
maintained; LCD Controller
and real-time clock are
functioning
Software
Power Down Mode 3
Short low pulse at
pin P3.2/INT0 or
real-time clock
wake-up interrupt
Hardware Reset
Oscillator is stopped;
contents of on-chip RAM,
XRAM and SFR’s are
maintained;
real-time clock is functioning
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