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參數(shù)資料
| 型號： | SAB-C505-LM |
| 廠商： | SIEMENS A G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-Bit CMOS Microcontroller |
| 中文描述： | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, MQFP-44 |
| 文件頁數(shù)： | 43/85頁 |
| 文件大小： | 487K |
| 代理商： | SAB-C505-LM |
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C505L
Data Sheet
41
06.99
10-Bit A/D Converter
The C505L includes a high performance / high speed 10-bit A/D-Converter (ADC) with 8 analog
input channels. It operates with a successive approximation technique and uses self calibration
mechanisms for reduction and compensation of offset and linearity errors. The A/D converter
provides the following features:
– 8 multiplexed input channels (port 1), which can also be used as digital inputs/outputs
– 10-bit resolution
– Single or continuous conversion mode
– Internal start-of-conversion trigger capability
– Interrupt request generation after each conversion
– Using successive approximation conversion technique via a capacitor array
– Built-in hidden calibration of offset and linearity errors
The 10-bit ADC uses two clock signals for operation: the conversion clock
f
ADC
(= 1/
t
ADC
) and the
input clock
f
IN
(= 1/
t
IN
).
f
ADC
is derived from the C505L system clock
f
OSC
which is applied at the
XTAL pins. The input clock
f
IN
is equal to
f
OSC
The conversion
f
ADC
clock is limited to a maximum
frequency of 2 MHz. Therefore, the ADC clock prescaler must be programmed to a value which
assures that the conversion clock does not exceed 2 MHz. The prescaler ratio is selected by the
bits ADCL1 and ADCL0 of SFR ADCON1.
Figure 19
10-Bit A/D Converter Clock Selection
MCS03867
32
16
8
4
÷
MUX
ADCL0
ADCL1
OSC
f
Clock Prescaler
Conversion Clock f
ADC
Input Clock
IN
f
A/D
Converter
Conditions:
f
ADCmax
= 2 MHz
f
IN
=f
OSC
=
1
CLP
÷
÷
÷
MCUSystemClock
Rate (
f
OSC
)
2 MHz
f
IN
[MHz]
Prescaler
Ratio
÷
4
÷
4
÷
4
÷
8
÷
8
÷
16
f
ADC
[MHz]
ADCL1
ADCL0
2
0.5
0
0
6 MHz
6
1.5
0
0
8 MHz
8
2
0
0
12 MHz
12
1.5
0
1
16 MHz
16
2
0
1
20 MHz
20
1.25
1
0
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