參數(shù)資料
型號: SAB-C161JI-32RF
廠商: INFINEON TECHNOLOGIES AG
英文描述: 16-Bit Single-Chip Microcontroller
中文描述: 16位單片機(jī)
文件頁數(shù): 84/89頁
文件大?。?/td> 876K
代理商: SAB-C161JI-32RF
C161CS/JC/JI-32R
C161CS/JC/JI-L
Data Sheet
80
V3.0, 2001-01
Figure 24
CLKOUT and READY
Notes
1)
Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).
2)
The leading edge of the respective command depends on RW-delay.
3)
READY sampled HIGH at this sampling point generates a READY controlled waitstate,
READY sampled LOW at this sampling point terminates the currently running bus cycle.
4)
READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or
WR).
5)
If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT
(e.g. because CLKOUT is not enabled), it must fulfill
t
37
in order to be safely synchronized. This is guaranteed,
if READY is removed in reponse to the command (see Note
4)
).
6)
Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may
be inserted here.
For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without
MTTC waitstate this delay is zero.
7)
The next external bus cycle may start here.
MCT04447
t
32
CLKOUT
ALE
Command
RD, WR
Sync
READY
Async
READY
t
33
t
29
t
30
t
31
t
34
7)
2)
3)
3)
t
35
t
36
t
35
t
36
t
58
t
59
3)
t
58
t
59
3)
t
37
5)
t
60
4)
see
6)
Running Cycle
1)
READY
Waitstate
MUX/Tristate
6)
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