參數(shù)資料
型號(hào): SAB-C161JI-32RF
廠商: INFINEON TECHNOLOGIES AG
英文描述: 16-Bit Single-Chip Microcontroller
中文描述: 16位單片機(jī)
文件頁(yè)數(shù): 78/89頁(yè)
文件大?。?/td> 876K
代理商: SAB-C161JI-32RF
C161CS/JC/JI-32R
C161CS/JC/JI-L
Data Sheet
74
V3.0, 2001-01
Data float after RdCS
(no RW-delay)
1)
Address hold after
RdCS, WrCS
Data hold after WrCS
t
68
SR
0 +
t
F
TCL - 20
+
2
t
A
+
t
F1)
ns
t
55
CC
-6 +
t
F
-6 +
t
F
ns
t
57
CC
6 +
t
F
TCL - 14 +
t
F
ns
1)
RW-delay and
t
A
refer to the next following bus cycle (including an access to an on-chip X-Peripheral).
2)
Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address changes before the end of RD have no impact on read cycles.
3)
These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
Demultiplexed Bus
(cont’d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2
t
A
+
t
C
+
t
F
(80 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 25 MHz
min.
Variable CPU Clock
1 / 2TCL = 1 to 25 MHz
min.
Unit
max.
max.
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