參數(shù)資料
型號(hào): SAB-C161JC-32RF
廠商: INFINEON TECHNOLOGIES AG
英文描述: 16-Bit Single-Chip Microcontroller
中文描述: 16位單片機(jī)
文件頁數(shù): 60/89頁
文件大?。?/td> 876K
代理商: SAB-C161JC-32RF
C161CS/JC/JI-32R
C161CS/JC/JI-L
Data Sheet
56
V3.0, 2001-01
AC Characteristics
Definition of Internal Timing
The internal operation of the C161CS/JC/JI is controlled by the internal CPU clock
f
CPU
.
Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus
cycles) operations.
The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called “TCL” (see
Figure 11
).
Figure 11
Generation Mechanisms for the CPU Clock
The CPU clock signal
f
CPU
can be generated from the oscillator clock signal
f
OSC
via
different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate
f
CPU
. This influence must
be regarded when calculating the timings for the C161CS/JC/JI.
Note: The example for PLL operation shown in the fig. above refers to a PLL factor of 4.
The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG
in register RP0H.7-5.
Upon a long hardware reset register RP0H is loaded with the logic levels present on the
upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins
MCT04338
f
OSC
f
CPU
Phase Locked Loop Operation
TCL
f
OSC
f
CPU
Direct Clock Drive
f
OSC
f
CPU
Prescaler Operation
TCL
TCL
TCL
TCL
TCL
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參數(shù)描述
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SAB-C161JC-LFCA 制造商:Infineon Technologies AG 功能描述:
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