參數(shù)資料
型號(hào): SAA7705H
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: Car radio Digital Signal Processor(DSP)(車(chē)載電臺(tái)數(shù)字信號(hào)處理器)
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP80
文件頁(yè)數(shù): 20/60頁(yè)
文件大小: 1857K
代理商: SAA7705H
1999 Aug 16
20
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
SAA7705H
8.6
The DSP core
This IC comprises a DSP core (the actual programmable
embedded calculating machine) that is adapted to the
required calculation power needed and as such is
optimized on area.
This DSP core is also known under the name EPICS6, of
which EPICS is the generic name of this type of DSP and
6 is the version number. This DSP is mainly a calculator
designed for real time processing (at f
s
= 38 or 44.1 kHz)
of the digitized audio data stream. A DSP is especially
suited to calculate the sum of products of the data words
representing the audiodata. See Chapter 13 fordocument
references on EPICS6.
8.7
External control pins and status register
The DSP core contains a 9-bit status register.
These 9 flags contain information which is used by the
conditional branch logic of the DSP core. For external use,
the flags F0, F1, F2 and F3 are available. Pins DSPIN1
and DSPIN2 control the status of the flags F0 and F1.
The two status flags F3 and F4 are controlled by the
DSP core and can be read via the pins DSPOUT1
and DSPOUT2. The function of each pin depends on the
DSP program. Another important flag is the I-flag. This flag
is an input flag and is set the moment new I
2
S-bus data or
another type of digital audio data is available to the
DSP core.
8.8
I
2
C-bus interface (pins SCL and SDA)
The I
2
C-bus format is described in “The I
2
C-bus and how
to use it” order no. 9398 393 40011.
For the external control of the SAA7705H a fast I
2
C-bus is
implemented. This is a 400 kHz bus which is downward
compatible with the standard 100 kHz bus.
There are three different types of control instructions:
Instructions to control the DSP program, programming
the coefficient RAM and reading the values of
parameters (level, multipath etc.)
Instructions to control the equalizer and to program the
equalizer coefficient RAM to be able to change the
centre frequency, gain and Q-factor of the equalizer
sections
Instructions controlling the I
2
S-bus data flow, such as
source selection, IAC control and clock speed.
The detailed description of the I
2
C-bus and the description
of the different bits in the memory map is given in
Chapter 12.
8.9
I
2
S-bus inputs and outputs
For communication with external digital sources, the
I
2
S-busdigitalinterfacebusisused.Itisaserial3-line bus,
having one line for data, one line for clock and one line for
the word select. For external digital sources the
SAA7705H acts as a slave, so the external source is
master and supplies the clock.
The I
2
S-bus input is capable of handling Philips I
2
S-bus
and LSB-justified formats of 16, 18 and 20-bit word sizes.
The selection of the digital audio format is described in
Tables 13 and 28. See Fig.9 for the general waveform
formats of the four possible formats.
The number of bit clock (BCK) pulses may vary in the
application. When the applied word length is shorter than
18 bits (internal resolution), the LSBs will get internally a
random value. When the applied word length exceeds
18 bits, the LSBs are skipped.
The input circuitry is limited in handling the number of BCK
pulses per WS period. The maximum allowed number of
bit clocks per WS channel (half of the symmetrical WS
period) is 128.
The DSP program is synchronized with the external
source via the word select signal. On every negative edge
of the IISWS the I-flag of the status register is set.
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