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參數(shù)資料
| 型號： | SAA7705H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Car radio Digital Signal Processor（DSP）(車載電臺數(shù)字信號處理器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 文件頁數(shù)： | 16/60頁 |
| 文件大?。?/td> | 1857K |
| 代理商： | SAA7705H |
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1999 Aug 16
16
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
SAA7705H
8.3.4
F
UNCTION OF PIN
POM
With pin POM it is possible to switch-off the reference
current of the DAC. The capacitor on pin POM
(see Fig.21) determines the time after which this current
has a soft switch-on. At power-on, the current audio signal
outputs are always muted. The external capacitor is
loaded in two stages via two different current sources.
The loading starts at a current level that is 9 times lower
than the load current after the voltage on pin POM has
risen above 1 V. This results in an almost dB-linear
behaviour. However, the DAC has an asymmetrical supply
and the DC output voltage will be half the supply voltage
under functional conditions. During start-up the output
voltage is not defined as long as the supply voltage is
below the threshold voltages of the transistors. A small
jump in DC is possible at start up. In this DC jump audio
components can be present.
8.3.5
P
OWER
-
OFF PLOP SUPPRESSION
To avoid plops in a power amplifier, the supply voltage
(3.3 V) for the analog part of the DAC can be supplied from
the 5 V supply via a transistor. A capacitor is connected to
V
DDA2
to maintain power to the analog part if the 5 V
supply is switched off fast. In this case the output voltage
will decrease gradually allowing the power amplifier some
extra time to switch-off without audible plops.
8.3.6
T
HE INTERNAL PIN
VREFDA
Using two internal resistors, half of the supply voltage
V
DDA2
is obtained and coupled to an internal buffer.
This reference voltage is used as a DC voltage for the
output operational amplifiers and as a reference for the
DAC. In order to obtain the lowest noise and to have the
best ripple rejection, a capacitor has to be connected
between this pin and ground.
8.3.7
I
NTERNAL
DAC
CURRENT REFERENCE
As a reference for the internal DAC current and also for the
DAC current source output, a current is drawn from
pin VREFDA to V
SSA2
(ground) via an internal resistor.
The value of this resistor determines also the DAC current
(absolute value). Consequently, the absolute value of the
current varies from device to device due to the spread of
the reference resistor value. This, however, has no
influence on the absolute output voltages because these
voltages are derived from a conversion of the DAC current
to the actual output voltage via internal resistors.
8.3.8
S
UPPLY OF THE ANALOG OUTPUTS
All the analog circuitry of the DACs and the operational
amplifiers are powered by 2 pins: V
DDA2
and V
SSA2
. V
DDA2
must have sufficient decoupling to prevent high THD and
to ensure a good Power Supply Rejection Ratio (PSRR).
The digital part of the DAC is fully supplied from the
DSP core supply.
8.4
Clock circuit and oscillator
The device has an on-chip oscillator. The block diagram of
this Pierce oscillator is shown in Fig.6. The active element
neededtocompensateforthelossresistanceofthecrystal
is the block G
m
. This block is placed between the external
pins OSCIN and OSCOUT. The gain of the oscillator is
internally controlled by the AGC block. A sine wave with a
peak-to-peak voltage close to the oscillator power supply
voltage is generated. The AGC block prevents clipping of
the sine wave and therefore the generation of harmonics
as much as possible. At the same time the voltage of the
sine wave is as high as possible which reduces the jitter
going from the sine wave to the clock signal.
8.4.1
S
UPPLY OF THE CRYSTAL OSCILLATOR
The supply of the oscillator is separated from the other
supplies. This minimizes the feedback from the ground
bounce of the chip to the oscillator circuit. Pin V
SS(OSC)
is
used as ground and pin V
DD(OSC)
as positive supply.
8.4.2
T
HE PHASE
-
LOCKED LOOP CIRCUIT TO GENERATE
THE
DSP
CLOCK AND OTHER DERIVED CLOCKS
A PLL circuit is used to generate the DSP clock and other
derived clocks.
The minimum equalizer clock frequency is 480f
s
.
If f
s
equals 44.1 kHz, this results in a minimum oscillator
frequency of 21.1687 MHz. Crystals for the crystal
oscillator in the range of twice the required DSP clock
frequency (approximately 40 MHz) are always
third-overtone crystals and must be manufactured on
customer demand. This makes these crystals expensive.
The PLL enables the use of a commonly available crystal
operating in fundamental mode. For this circuit a
11.2896 MHz(256
×
44.1 kHz)crystalischosen.Thistype
of crystal is widely used.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7706H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Car radio Digital Signal Processor (DSP) |
| SAA7706H/N107 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DIGITAL SIGNAL PROCESSOR RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| SAA7706H/N107,518 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DIRAC-1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| SAA7706H/N107,557 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DIGITAL SIGNAL RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| SAA7706H/N107S,518 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC CAR RADIO DIGITAL SIGNAL PROCESSOR RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
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