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參數(shù)資料
| 型號： | SAA7705H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Car radio Digital Signal Processor（DSP）(車載電臺數(shù)字信號處理器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 文件頁數(shù)： | 18/60頁 |
| 文件大小： | 1857K |
| 代理商： | SAA7705H |
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1999 Aug 16
18
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
SAA7705H
Fig.7 Programmable PLL for DSP clock generation.
handbook, full pagewidth
MGM127
OSCIN
OSCOUT
VDD(OSC)
VSS(OSC)
PLL-DIV(0)
PLL-DIV(1)
PLL-DIV(2)
PLL-DIV(3)
11.2896 MHz
OSCILLATOR
÷
256
÷
2
÷
2
÷
2
÷
2
÷
N
×
Iref
Idelay
44.1 kHz
70 to
130 MHz
27.1656 MHz
54.3312 MHz
N = 154
clock
clock
from
DCSCTR
register
PHASE
DETECTOR
LOOP
FILTER
CURRENT CONTROLLED OSCILLATOR
8.5
Equalizer accelerator circuit
8.5.1
I
NTRODUCTION
The Equalizer accelerator (EQ) circuit is an equalizer
circuit used as a hardware accelerator to the DSP core.
Its inputs and outputs are stored in registers of the
DSP core (these registers provide the digital data
communication between the equalizer and the DSP core).
The flag that starts the DSP program, refreshes the EQ
input and output registers and starts the EQ controller.
The EQ circuit contains one second-order filter data path
that is twenty-fold multiplexed. With this circuit, a
two-channel equalizer of 10 second-order sections per
channel or a four-channel equalizer of 5 second-order
sections per channel can be realized.
The centre frequency, gain and Q-factor of all
20 second-order sections can be set independently from
each other. Every section is followed by a variable
attenuation of 0 or 6 dB. Per section, 4 bytes are needed
to store the settings. During an audio sample period, all
settings are read as 16-bit words in 80 read accesses to
the coefficient memory.
8.5.2
EQ
CIRCUIT OVERVIEW
This EQ circuit contains the following parts:
A second-order filter data path, with programmable
coefficients and with 40 state registers, supporting
storage of the two filter states for 20 multiplexed filters;
this part is clocked by a gated clock
Signal routing around this filter data path, consisting of:
– buses and selectors to configure the 20 filter sections
for two or four channels;
– inputandoutputregisters,withproperinterfacingwith
the DSP core and with conversions between parallel
and serial formats.
A coefficient memory, to be loaded via the I
2
C-bus
interface
A controller, started by the write pulse for input and
output registers, that controls the signal routing, controls
the clock for the filter data path, addresses the
coefficient memory and controls its programming.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7706H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Car radio Digital Signal Processor (DSP) |
| SAA7706H/N107 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DIGITAL SIGNAL PROCESSOR RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| SAA7706H/N107,518 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DIRAC-1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| SAA7706H/N107,557 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DIGITAL SIGNAL RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| SAA7706H/N107S,518 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC CAR RADIO DIGITAL SIGNAL PROCESSOR RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
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