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參數(shù)資料
| 型號： | SAA2013 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Adaptive allocation and scaling for PASC coding in DCC systems |
| 中文描述： | 自適應分配和戴納信貸混凝劑縮放系統(tǒng)編碼 |
| 文件頁數(shù)： | 8/32頁 |
| 文件大小： | 137K |
| 代理商： | SAA2013 |
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May 1994
8
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
Fig.5 SLEEP and RESET timing.
handbook, full pagewidth
MGB358
td
th
SLEEP
RESET
CLK24
Low-power decode mode
Low-power decode mode is made available by connecting
the LOWPWR pin to V
DD
. With LOWPWR = V
DD
,
low-power decode mode is entered 9 cycles of CLK24
after the SLEEP input is taken HIGH. In low-power decode
mode, the L3 bus connections are connected straight
trough the SAA2013, which is effectively bypassed. The
compensation delay connection between pins FDAI and
FDAO is no longer needed by the SAA2003, and CLK24
and FS256 are stopped internally to the SAA2013.
To get out of low-power decode mode, it is necessary to
take SLEEP LOW, FDIR LOW, and FRESET HIGH (in a
normal application taking FDIR LOW and FRESET HIGH
can be achieved by setting SAA2003 into encode mode),
SAA2013 then performs an internal reset, and defaults to
normal decode mode. The RESET pin does not reset the
circuit from low-power decode mode.
Power-On Reset (POR)
When low-power decode mode is enabled
(LOWPWR = V
DD
), a power-on reset circuit is required to
ensure that the internal clocks are connected correctly at
power-on. A suitable circuit is shown in Fig.6. This circuit
will correctly reset the internal clock connection provided
that the nominal value of the V
DD
supply is reached within
40 ms at power-on.
Encode mode
In encode mode the SAA2013 receives sub-band filtered
samples from SAA2003 on the FDAI pin. The SAA2013
has to collect a complete frame of sub-band data before
the allocation and scale factor information can be
calculated. So that the allocation and scale factor
information is available in the same time frame as the
audio samples at the output, the sub-band filtered samples
are delayed by 480 FDWS periods.
One FDWS period is equal to
where f
s
is the audio
sample rate of 32, 44.1 or 48 kHz. The delayed samples
are passed to the codec part of SAA2003 on the
FDAO pin.
handbook, halfpage
MGB359
VDD
150
k
1 F
POR
VSS
VDD
VSS
Fig.6 POR circuit.
1
f
s
---
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