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參數(shù)資料
| 型號： | SAA2013 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Adaptive allocation and scaling for PASC coding in DCC systems |
| 中文描述： | 自適應(yīng)分配和戴納信貸混凝劑縮放系統(tǒng)編碼 |
| 文件頁數(shù)： | 14/32頁 |
| 文件大?。?/td> | 137K |
| 代理商： | SAA2013 |
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May 1994
14
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
Since the two bytes of status information are sampled
separately, the bytes may result from different sub-band
frames.
The only valid bit rate code for the SAA2013 is 1100.
The sample frequency indication is shown in Table 7.
Table 7
Sample frequency indication.
Ready-to-receive S or E indicates whether the SAA2013 is
ready-to-receive new settings or extended settings from
the microcontroller. This should be checked before
sending new information.
For details of the MODE, SYNC, CLKOK and transparent
bits, refer to the “SAA2003 data sheet”
The emphasis indication can be used to apply the correct
de-emphasis. In encode SAA2013 will correct the
calculated allocation if
50
15
μ
s emphasis is applied. When
“CCITT J.17” emphasis is applied, the bit allocation
remains the same as when no emphasis is applied.
The 2 bytes of the status are ‘sampled’ at different
moments. So the information may not result from the same
sub-band frame.
When making repeated status reads (for instance reading
the RTRS/RTRE flags before sending settings or extended
settings), the microcontroller
must
send an address
before each status read, to ensure that the byte counter in
the interface is reset to logic 0. If this is not done, then the
peak data will be read. Conversely, it is important
not
to
send a new address after a status read if the peak data is
required.
P
EAK READ
Peak information is read by clocking a further 4 bytes of
data after a status read. The data format is shown in
Figs 11 and 12. Bits B17 to B31 contain a 15-bit unsigned
peak, LSB first, channel indicated by bit B16. Bits B33 to
B47 contain a 15-bit unsigned peak, channel indicated by
bit B32.
The peak data is delayed by 1 read period. If for example
the microcontroller reads peak level data every 50 ms, the
peak data sourced by SAA2013 will be 50 ms old. Also it
BIT 11
BIT 10
SAMPLE FREQUENCY
0
0
1
1
0
1
0
1
44.1 kHz; default
48.0 kHz
32.0 kHz
do not use
is possible that peak data may contain an additional delay
of 1 column (667
μ
s minimum at 48 kHz, 1 ms maximum
at 32 kHz). If the microcontroller attempts to read peak
level data with a delay of less than 1 column, the peak level
data from the previous reading will be repeated. Normally
the microcontroller should allow at least 1 ms between
reads. There is also a delay required between peak data
words (Fig.13).
If the SAA2013 does not have peak data available (for
instance the microcontroller attempts two reads in very
quick succession), it will return all peak data bits set to
logic 0. The microcontroller can detect if valid peak data
has been returned by inspecting bits T16 and T32. If both
bits are set to logic 0 the data is not valid.
handbook, halfpage
0 0 1 0 0 0 1 1
STATUS MSB
PEAK BYTE 1
PEAK BYTE 3
STATUS LSB
PEAK BYTE 0
PEAK BYTE 2
LSB
MGB364
Fig.11 Peak level read format; SAA2013 to
microcontroller.
handbook, halfpage
M
L
16
15-bit peak
channel
indicator
bits 17 to 31
M
L
32
15-bit peak
channel
indicator
bits 33 to 47
MGB365
Fig.12 Peak level format.
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