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參數(shù)資料
| 型號： | SAA2013 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Adaptive allocation and scaling for PASC coding in DCC systems |
| 中文描述： | 自適應(yīng)分配和戴納信貸混凝劑縮放系統(tǒng)編碼 |
| 文件頁數(shù)： | 7/32頁 |
| 文件大?。?/td> | 137K |
| 代理商： | SAA2013 |
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May 1994
7
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
PASC processor
The PASC processor is a dedicated Digital Signal
Processor (DSP) engine which efficiently codes digital
audio data at a bit rate of 384 kbits/s without affecting the
sound quality. This is achieved using an efficient adaptive
data notation and by only encoding the audio information
which can be heard by the human ear.
The audio data is split into 32 equal sub-bands during
encoding. For each of the sub-bands a masking threshold
is calculated. The samples from each of the sub-bands are
included in the PASC data with an accuracy that is
determined by the available bit-pool and by the difference
between the signal power and the masking threshold for
that sub-band. In decode, the sub-band signals are
reconstructed into the full bandwidth audio signal.
The stereo filter codec performs the splitting (encoding)
and reconstruction (decoding), including the necessary
formatting functions. During encoding, the adaptive
allocation and scaling circuit calculates the required
accuracy (bit allocation) and scale factors of the
sub-band samples.
Decode/encode control
Selection of decode or encode is controlled using FRESET
and FDIR. FRESET causes a general reset. The FDIR
signal is sampled at the falling edge of the FRESET signal
to determine the operation mode. When FDIR is HIGH,
SAA2013 is in decode mode. When FDIR is LOW the
SAA2013 is in encode mode. See Fig.4.
Fig.4 FDIR and FRESET timing.
handbook, full pagewidth
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FRESET
FDIR
tsu
th
MGB357
Reset
When used with low-power mode disabled
(LOWPWR = V
SS
), and with the SLEEP input LOW,
SAA2013 is reset if the RESET pin is held HIGH for at least
5 periods of the CLK24 clock, see Fig.5. SAA2013 defaults
to decode mode. When in low-power mode, the RESET
pin is disabled.
Sleep mode
Sleep mode is entered by taking the SLEEP input HIGH
with the LOWPWR pin connected to V
SS
; CLK24 and
FS256 are stopped internally to the SAA2013, the 3-state
buffers will have a high impedance, and outputs will freeze
in the same state as just before the sleep mode became
active (clocks stopped). To come out of sleep mode, the
SLEEP input must be taken LOW again. To clear data
present from before sleep was entered, this should be
followed by a reset, see Fig.5.
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