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參數(shù)資料
| 型號： | S71PL032J40 |
| 廠商： | Spansion Inc. |
| 英文描述： | STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM |
| 中文描述： | 堆疊式多芯片產(chǎn)品，閃存和RAM |
| 文件頁數(shù)： | 73/196頁 |
| 文件大?。?/td> | 5729K |
| 代理商： | S71PL032J40 |
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August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
73
A d v a n c e I n f o r m a t i o n
Program/Erase Resume (Note 12)
1
BA
30
CFI Query (Note 13)
1
55
98
Accelerated Program (Note 15)
2
XX
A0
PA
PD
Unlock Bypass Entry (Note 15)
3
555
AA
2AA
55
555
20
Unlock Bypass Program (Note 15)
2
XX
A0
PA
PD
Unlock Bypass Erase (Note 15)
2
XX
80
XX
10
Unlock Bypass CFI (Notes
13
,
15
)
1
XX
98
Unlock Bypass Reset (Note 15)
2
XXX
90
XXX
00
Table 18. Sector Protection Command Definitions
Command
(Notes)
C
1
Bus Cycles (Notes
1
-
4
)
Addr
Data
Addr
Data Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Reset
Secured Silicon
Sector Entry
Secured Silicon
Sector Exit
Secured Silicon
Protection Bit
Program (Notes
5
,
6
)
Secured Silicon
Protection Bit
Status
Password Program
(Notes
5
,
7
,
8
)
XXX
F0
3
555
AA
2AA
55
555
88
4
555
AA
2AA
55
555
90
XX
00
6
555
AA
2AA
55
555
60
OW
68
OW
48
OW
RD(0)
5
555
AA
2AA
55
555
60
OW
48
OW
RD(0)
4
555
AA
2AA
55
555
38
XX[0-3]
PD[0-3]
Table 17. Memory Array Command Definitions
Command (Notes)
Bus Cycles (Notes
1
–
4
)
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Legend:
BA = Address of bank switching to autoselect mode, bypass
mode, or erase operation. Determined by PL127J: Amax:A20,
PL064J: Amax:A19, PL032J: Amax:A18.
PA = Program Address (Amax:A0). Addresses latch on falling
edge of WE# or CE# pulse, whichever happens later.
PD = Program Data (DQ15:DQ0) written to location PA. Data
latches on rising edge of WE# or CE# pulse, whichever happens
first.
Notes:
1.
See Table
1
for description of bus operations.
2.
All values are in hexadecimal.
3.
Shaded cells in table denote read cycles. All other cycles are
write operations.
4.
During unlock and command cycles, when lower address bits
are 555 or 2AAh as shown in table, address bits higher than
A11 (except where BA is required) and data bits higher than
DQ7 are don’t cares.
5.
No unlock or command cycles required when bank is reading
array data.
6.
The Reset command is required to return to reading array
(or to erase-suspend-read mode if previously in Erase
Suspend) when bank is in autoselect mode, or if DQ5 goes
high (while bank is providing status information).
7.
Fourth cycle of autoselect command sequence is a read
cycle. System must provide bank address to obtain
manufacturer ID or device ID information. See Autoselect
Command Sequence
section
for more information.
8.
The data is C4h for factory and customer locked, 84h for
factory locked and 04h for not locked.
RA = Read Address (Amax:A0).
RD = Read Data (DQ15:DQ0) from location RA.
SA = Sector Address (Amax:A12) for verifying (in autoselect
mode) or erasing.
WD = Write Data. See “Configuration Register” definition for
specific write data. Data latched on rising edge of WE#.
X = Don’t care
9.
The data is 00h for an unprotected sector group and 01h for
a protected sector group.
10. Device ID must be read across cycles 4, 5, and 6. PL127J
(X0Eh = 2220h, X0Fh = 2200h),PL064J (X0Eh = 2202h,
X0Fh = 2201h), PL032J (X0Eh = 220Ah, X0Fh = 2201h).
11. System may read and program in non-erasing sectors, or
enter autoselect mode, when in Program/Erase Suspend
mode. Program/Erase Suspend command is valid only
during a sector erase operation, and requires bank address.
12. Program/Erase Resume command is valid only during Erase
Suspend mode, and requires bank address.
13. Command is valid when device is ready to read array data or
when device is in autoselect mode.
14.
WP#/ACC
must be at V
ID
during the entire operation of
command.
15. Unlock Bypass Entry command is required prior to any
Unlock Bypass operation. Unlock Bypass Reset command is
required to return to the reading array.
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