- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374670 > S71PL032J40 (Spansion Inc.) STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM PDF資料下載
參數(shù)資料
| 型號： | S71PL032J40 |
| 廠商： | Spansion Inc. |
| 英文描述： | STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM |
| 中文描述： | 堆疊式多芯片產(chǎn)品，閃存和RAM |
| 文件頁數(shù)： | 188/196頁 |
| 文件大?。?/td> | 5729K |
| 代理商： | S71PL032J40 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁當(dāng)前第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁
188
pSRAM Type 1
pSRAM_Type01_12_A0 June 8, 2004
A d v a n c e I n f o r m a t i o n
Power Savings Modes (For 16M Page Mode, 32M and 64M Only)
There are several power savings modes.
Partial Array Self Refresh
Temperature Compensated Refresh (64M)
Deep Sleep Mode
Reduced Memory Size (32M, 16M)
The operation of the power saving modes ins controlled by the settings of bits
contained in the Mode Register. This definition of the Mode Register is shown in
Figure 93 and the various bits are used to enable and disable the various low
power modes as well as enabling Page Mode operation. The Mode Register is set
by using the timings defined in Figure xxx.
Partial Array Self Refresh (PAR)
In this mode of operation, the internal refresh operation can be restricted to a
16Mb, 32Mb, or 48Mb portion of the array. The array partition to be refreshed is
determined by the respective bit settings in the Mode Register. The register set-
tings for the PASR operation are defined in Table xxx. In this PASR mode, when
ZZ# is active low, only the portion of the array that is set in the register is re-
freshed. The data in the remainder of the array will be lost. The PASR operation
mode is only available during standby time (ZZ# low) and once ZZ# is returned
high, the device resumes full array refresh. All future PASR cycles will use the
contents of the Mode Register that has been previously set. To change the ad-
dress space of the PASR mode, the Mode Register must be reset using the
previously defined procedures. For PASR to be activated, the register bit, A4Must
be set to a one (1) value, “PASR Enabled”. If this is the case, PASR will be acti-
vated 10 μs after ZZ# is brought low. If the A4 register bit is set equal to zero
(0), PASR will not be activated.
Temperature Compensated Refresh (for 64Mb)
In this mode of operation, the internal refresh rate can be optimized for the op-
eration temperature used and this can then lower standby current. The DRAM
array in the PSRAM must be refreshed internally on a regular basis. At higher
temperatures, the DRAM cell must be refreshed more often than at lower tem-
peratures. By setting the temperature of operation in the Mode Register, this
refresh rate can be optimized to yield the lowest standby current at the given op-
erating temperature. There are four different temperature settings that can be
programmed in to the PSRAM. These are defined in Figure 93.
Deep Sleep Mode
In this mode of operation, the internal refresh is turned off and all data integrity
of the array is lost. Deep Sleep is entered by bringing ZZ# low with the A4 reg-
ister bit set to a zero (0), “Deep Sleep Enabled”. If this is the case, Deep Sleep
will be entered 10 μs after ZZ# is brought low. The device will remain in this mode
as long as ZZ# remains low. If the A4 register bit is set equal to one (1), Deep
Sleep will not be activated.
Reduced Memory Size (for 32M and 16M)
In this mode of operation, the 32Mb PSRAM can be operated as a 8Mb or 16Mb
device. The mode and array size are determined by the settings in the VA register.
The VA register is set according to the following timings and the bit settings in
the table “Address Patterns for RMS”. The RMS mode is enabled at the time of ZZ
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S71PL032J40-07 | STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM |
| S71PL032J40-0K | STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM |
| S71PL032J80 | STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM |
| S71PL032J80-07 | STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM |
| S71PL032J80-0P | STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S71PL032J40-07 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM |
| S71PL032J40-0K | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM |
| S71PL032J40BAW0Z0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Based MCPs |
| S71PL032J40BAW0Z2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Based MCPs |
| S71PL032J40BAW0Z3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Based MCPs |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。