參數(shù)資料
型號(hào): S71GL064A08BAW0B2
廠商: SPANSION LLC
元件分類: 存儲(chǔ)器
英文描述: Stacked Multi-Chip Product (MCP) Flash Memory and RAM
中文描述: SPECIALTY MEMORY CIRCUIT, PBGA56
封裝: 7 X 9 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-56
文件頁數(shù): 100/102頁
文件大?。?/td> 1606K
代理商: S71GL064A08BAW0B2
100
S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005
A d v a n c e I n f o r m a t i o n
Figure 36. Timing Waveform of Write Cycle(2) (CS# controlled, if BYTE# is Low, Ignore UB#/LB# Timing)
Notes:
1. A write occurs during the overlap (t
WP
) of low CS1# and low WE#. A write begins when CS1# goes low and WE#
goes low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double
byte operation. A write ends at the earliest transition when CS1# goes high and WE# goes high. The t
WP
is
measured from the beginning of write to the end of write.
2. t
CW
is measured from the CS1# going low to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as CS1# or WE#
going high.
Figure 37. Timing Waveform of Write Cycle(3) (UB#, LB# controlled)
High-Z
High-Z
t
WC
t
CW(2)
t
AW
t
BW
t
WP(1)
t
DH
t
DW
t
WR(4)
t
AS(3)
Address
CS1#
CS2
UB#, LB#
WE#
Data in
Data out
Data Valid
High-Z
High-Z
t
WC
t
CW(2)
t
BW
t
WP(1)
t
DH
t
DW
t
WR(4)
t
AW
t
AS(3)
t
CW(2)
Address
CS1#
CS2
UB#, LB#
WE#
Data in
Data out
Data Valid
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