參數(shù)資料
型號： S29NS-P
廠商： Spansion Inc.
英文描述： MirrorBit Flash Family
中文描述： MirrorBit閃存系列
文件頁數(shù)： 79/86頁
文件大?。?/td> 2234K
代理商： S29NS-P
February 20, 2007 S29NS-P_00_A1
S29NS-P MirrorBit
TM
Flash Family
79
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
BA = Bank Address. NS128P = A22
–
A20, and A19; NS064P = A21, A20
–
A18; NS256P = A23
–
A20.CR = Configuration Register data
bits D15
–
D0.
WBL = Write Buffer Location. Address must be within the same write buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
Notes
1. See
Table 6.1
for description of bus operations.
2. All values are in hexadecimal.
3. Except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the Autoselect commands, fourth cycle of
the configuration register verify and password verify commands, and any cycle reading at RD(0) and RD(1).
4. Data bits DQ15
–
DQ8 are don’t care in command sequences, except for RD, PD, WD, PWD, and PWD3
–
PWD0.
5. Unless otherwise noted, address bits Amax
–
A14 are don’t cares.
6. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The
system must write the reset command to return the device to reading array data.
7. No unlock or command cycles required when bank is reading array data.
8. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when
a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information) or performing sector lock/unlock.
9. The fourth cycle of the autoselect address is a read cycle. The system must provide the bank address.
10.(BA) + 0Eh ----> For NS128 = 43h, NS256 = 41h, NS512 = 3Fh (BA) + 0Fh ----> For NS128/256/512 = 00h
11.The data is 0000h for an unlocked sector and 0001h for a locked sector
12.See
Table 6.12,
Autoselect Addresses on page 34
.
13.The Unlock Bypass command sequence is required prior to this command sequence.
14.The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode.
15.The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The
Program/Erase Suspend command is valid only during a program/ erase operation, and requires the bank address.
16.The Program/Erase Resume command is valid only during the Program/Erase Suspend mode, and requires the bank address.
17.The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The maximum
number of cycles in the command sequence is 37.
18.Write Buffer Programming can be initiated after Unlock Bypass Entry.
19.Data is always output at the rising edge of clock.
20.Do not enter wrong address or data cycles.
21.Do not use 0x30 for CR data (otherwise in the erase suspend --> CR read or set sequence, the device will go into erase resume instead
of CR read or set).
22.Software reset is needed after CR read (otherwise the device is still in CR read mode).
23.When device is in Unlock Bypass mode, do not enter another command before Unlock Bypass reset command is issued).
24.Configuration Registers can not be programmed out of order. CR0 must be programmed prior to CR01 otherwise the configuration
registers retain their previous settings.
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