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參數(shù)資料
| 型號： | S29NS-P |
| 廠商： | Spansion Inc. |
| 英文描述： | MirrorBit Flash Family |
| 中文描述： | MirrorBit閃存系列 |
| 文件頁數(shù)： | 50/86頁 |
| 文件大?。?/td> | 2234K |
| 代理商： | S29NS-P |
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50
S29NS-P MirrorBit
TM
Flash Family
S29NS-P_00_A1 February 20, 2007
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
6.6
Simultaneous Read/Write
The simultaneous read/write feature allows the host system to read data from one bank of memory while
programming or erasing another bank of memory. An erase operation may also be suspended to read from or
program another location within the same bank (except the sector being erased).
Figure 10.21
,
Back-to-Back
Read/Write Cycle Timings
, shows how read and write cycles may be initiated for simultaneous operation with
zero latency. Refer to the
DC Characteristics
table for read-while-program and read-while-erase current
specification.
6.7
Writing Commands/Command Sequences
When the device is in Asynchronous read, only Asynchronous write operations are allowed. During an
asynchronous write operation, the system must drive CE# and WE# to V
IL
and OE# to V
IH
when providing an
address, command, and data. Addresses are latched on the rising edge of AVD#, while data is latched on the
rising edge of WE#. An erase operation can erase one sector, multiple sectors, or the entire device.
Table 5.1
–
Table 5.3
indicate the address space that each sector occupies. The device address space is divided into
sixteen banks: for NS512P, all 16 banks contain 64-Kword sectors while for NS256P and NS128P, Banks 0
through 14 contain only 64 Kword sectors, Bank 15 contains 16-Kword boot sectors in addition to 64 Kword
sectors. A
bank address
is the set of address bits required to uniquely select a bank. Similarly, a
sector
address
is the address bits required to uniquely select a sector. I
CC2
in the
DC Characteristics
section
represents the active current specification for the write mode.
AC Characteristics-Synchronous
and
AC
Characteristics-Asynchronous
contain timing specification tables and timing diagrams for write operations.
6.8
Handshaking
The handshaking feature allows the host system to detect when data is ready to be read by simply monitoring
the RDY pin which is a dedicated output and is controlled by CE#.
6.9
Hardware Reset
The RESET# input provides a hardware method of resetting the device to reading array data. When RESET#
is driven low for at least a period of t
RP
, the device immediately terminates any operation in progress, tristates
all outputs, resets the configuration register, and ignores all read/write commands for the duration of the
RESET# pulse. The device also resets the internal state machine to reading array data.
To ensure data integrity the operation that was interrupted should be reinitiated once the device is ready to
accept another command sequence.
When RESET# is held at V
SS
, the device draws CMOS standby current (I
CC4
). If RESET# is held at V
IL
, but
not at V
SS
, the standby current is greater.
RESET# may be tied to the system reset circuitry which enables the system to read the boot-up firmware
from the Flash memory upon a system reset.
See
Figures
10.5
and
10.11
for timing diagrams.
6.10
Software Reset
Software reset is part of the command set (see
Table 11.1
) that also returns the device to array read mode
and must be used for the following conditions:
1. to exit Autoselect mode
2. when DQ5 goes high during write status operation that indicates program or erase cycle was not
successfully completed
3. exit sector lock/unlock operation.
4. to return to erase-suspend-read mode if the device was previously in Erase Suspend mode.
5. after any aborted operations
6. exiting read configuration registration Mode
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