參數(shù)資料
型號: S29GL064N11FAI040
廠商: Spansion Inc.
英文描述: 64 Megabit, 32 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 110 nm MirrorBit Process Technology
中文描述: 64兆,32兆位3.0伏只頁面模式閃存具有110納米MirrorBit工藝技術(shù)
文件頁數(shù): 54/79頁
文件大小: 2191K
代理商: S29GL064N11FAI040
54
S29GL-N MirrorBit
Flash Family
S29GL-N_01_09 November 16, 2007
D a t a
S h e e t
Table 10.4
Sector Protection Commands (x8)
Command Sequence
(Notes)
Command Set Entry
(Note 5)
Program
(Note 6)
Read
(Note 6)
Command Set Exit
(Note 7)
Command Set Entry
(Note 5)
Program
(Note 8)
C
Bus Cycles (Notes
2
5
)
3rd/10th
Addr
Data
1st/8th
Addr
2nd/9th
4th/11th
Addr
5th
6th
7th
Data
Addr
Data
Data
Addr
Data
Addr
Data
Addr
Data
L
R
B
3
AAA
AA
555
55
AAA
40
2
1
XXX
00
A0
Data
XXX
Data
2
XXX
90
XXX
00
P
P
3
AAA
AA
555
55
AAA
60
2
XXX
00
07
00
05
A0
PWAx
01
PWDx
PWD1
Read
(Note 9)
8
PWD0
PWD7
25
PWD5
02
PWD2
03
PWD3
04
PWD4
05
PWD5
06
PWD6
Unlock
(Note 10)
11
00
06
03
00
07
PWD0
PWD7
01
00
PWD1
29
02
PWD2
03
PWD3
04
PWD4
PWD6
Command Set Exit
(Note 7)
Command Set Entry
(Note 5)
PPB Program
(Note 11)
All PPB Erase
(Notes
11
,
12
)
PPB Status Read
Command Set Exit
(Note 7)
Command Set Entry
(Note 5)
PPB Lock Bit Set
PPB Lock Bit Status
Read
Command Set Exit
(Note 7)
Command Set Entry
(Note 5)
DYB Set
DYB Clear
DYB Status Read
Command Set Exit
(Note 7)
2
XX
90
XX
00
N
S
(
3
AAA
AA
555
55
AAA
C0
2
XXX
A0
SA
00
2
XXX
80
00
30
1
SA
RD(0)
2
XXX
90
XXX
00
G
S
F
3
AAA
AA
555
55
AAA
50
2
XXX
A0
XXX
00
1
XXX
RD(0)
2
XXX
90
XX
00
V
P
(
3
AAA
AA
555
55
AAA
E0
2
2
1
XXX
XXX
SA
A0
A0
SA
SA
00
01
RD(0)
2
XXX
90
XXX
00
Legend
X = Don’t care.
RA = Address of the memory location to be read.
SA = Sector Address. Any address that falls within a specified sector. See
Tables
8.2
8.8
for sector address ranges.
PWA = Password Address. Address bits A1 and A0 are used to select each 16-
bit portion of the 64-bit entity.
PWD = Password Data.
RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 0. If unprotected,
DQ0 = 1.
Notes
1. All values are in hexadecimal.
2. Shaded cells indicate read cycles.
3. Address and data bits not specified in table, legend, or notes are don’t
cares (each hex digit implies 4 bits of data).
4. Writing incorrect address and data values or writing them in the improper
sequence may place the device in an unknown state. The system must
write the reset command to return the device to reading array data.
5. Entry commands are required to enter a specific mode to enable
instructions only available within that mode.
6. No unlock or command cycles required when bank is reading array data.
7. Exit command must be issued to reset the device into read mode; device
may otherwise be placed in an unknown state.
8. Entire two bus-cycle sequence must be entered for each portion of the
password.
9. Full address range is required for reading password.
10.Password may be unlocked or read in any order. Unlocking requires the full
password (all seven cycles).
11.ACC must be at V
IH
when setting PPB or DYB.
12.“All PPB Erase” command pre-programs all PPBs before erasure to prevent
over-erasure.
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