參數(shù)資料
型號: S25FL008A0LMAI000
廠商: SPANSION LLC
元件分類: DRAM
英文描述: 8-Megabit CMOS 3.0 Volt Flash Memory with 50 MHz SPI (Serial Peripheral Interface) Bus
中文描述: 8M X 1 FLASH 3V PROM, PDSO8
封裝: 0.208 INCH, PLASTIC, SOP-8
文件頁數(shù): 21/32頁
文件大?。?/td> 719K
代理商: S25FL008A0LMAI000
August31,2006 S25FL008A_00_B0
S25FL008A
19
D a t a
S h e e t
Figure 9.8
Page Program (PP) Command Sequence
9.9
Sector Erase (SE)
The Sector Erase (SE) command sets all bits at all addresses within a specified sector to a logic 1. A WREN
command is required prior to writing the PP command.
The host system must drive CS# low, and then write the SE command plus three address bytes on SI. Any
address within the sector (see
Table 7.1 on page 11
) is a valid address for the SE command. CS# must be
driven low for the entire duration of the SE sequence. The command sequence is shown in
Figure 9.9
and
Table 9.4
.
The host system must drive CS# high after the device has latched the 8th bit of the SE command, otherwise
the device does not execute the command. The SE operation begins as soon as CS# is driven high. The
device internally controls the timing of the operation, which requires a period of t
SE
. The Status Register may
be read to check the value of the Write In Progress (WIP) bit while the SE operation is in progress. The WIP
bit is 1 during the SE operation, and is 0 when the operation is completed. The device internally resets the
Write Enable Latch to 0 before the operation completes (the exact timing is not specified).
The device does not execute an SE command that specifies a sector that is protected by the Block Protect
bits (BP2:BP0) (see
Table 7.1 on page 11
).
Figure 9.9
Sector Erase (SE) Command Sequence
0
3
4
33
3
2
3
1
3
0
29
2
8
10
9
8
7
6
5
4
3
2
1
3
5
3
6
3
7
38
3
9
46
45
44
4
3
42
41
40
47 4
8
49 50
51
52 5
3
54
55
2
3
2
2
2
2
2
2
8
2
2
3
22 21
3
2
1
0
7
6
5
4
3
2
1
0
D
a
t
a
Byte 1
24-Bit Addre
ss
Comm
a
nd
D
a
t
a
Byte 2
D
a
t
a
Byte
3
D
a
t
a
Byte 256
M
S
B
M
S
B
M
S
B
M
S
B
M
S
B
S
CK
S
I
S
CK
S
I
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
C
S
#
C
S
#
Mode 0
Mode
3
C
S
#
S
CK
S
I
S
O
M
S
B
Comm
a
nd
24-
b
it Addre
ss
0
1
2
3
4
5
6
7
8
9
10
2
8
29
3
0
3
1
2
3
22
21
3
2
1
0
Hi-Z
Mode 0
Mode
3
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