參數(shù)資料
型號: S25FL008A0LMAI000
廠商: SPANSION LLC
元件分類: DRAM
英文描述: 8-Megabit CMOS 3.0 Volt Flash Memory with 50 MHz SPI (Serial Peripheral Interface) Bus
中文描述: 8M X 1 FLASH 3V PROM, PDSO8
封裝: 0.208 INCH, PLASTIC, SOP-8
文件頁數(shù): 13/32頁
文件大?。?/td> 719K
代理商: S25FL008A0LMAI000
August31,2006 S25FL008A_00_B0
S25FL008A
11
D a t a
S h e e t
7.6
Data Protection Modes
Spansion SPI Flash memory devices provide the following data protection methods:
The Write Enable (WREN) command:
Must be written prior to any command that modifies data. The
WREN command sets the Write Enable Latch (WEL) bit. The WEL bit resets (disables writes) on
power-up
or after the device completes the following
commands
:
– Page Program (PP)
– Sector Erase (SE)
– Bulk Erase (BE)
– Write Disable (WRDI)
– Write Status Register (WRSR)
Software Protected Mode (SPM):
The Block Protect (BP2, BP1, BP0) bits define the section of the
memory array that can be read but not programmed or erased.
Table 7.1
shows the sizes and address
ranges of protected areas that are defined by Status Register bits BP2:BP0.
Hardware Protected Mode (HPM):
The Write Protect (W#) input and the Status Register Write Disable
(SRWD) bit together provide write protection.
Clock Pulse Count:
The device verifies that all program, erase, and Write Status Register commands
consist of a clock pulse count that is a multiple of eight before executing them.
7.7
Hold Mode (HOLD#)
The Hold input (HOLD#) stops any serial communication with the device, but does not terminate any Write
Status Register, program or erase operation that is currently in progress.
The Hold mode starts on the falling edge of HOLD# if SCK is also low (see
Figure 7.1, on page 12
, standard
use). If the falling edge of HOLD# does not occur while SCK is low, the Hold mode begins after the next falling
edge of SCK (non-standard use).
The Hold mode ends on the rising edge of HOLD# signal (standard use) if SCK is also low. If the rising edge
of HOLD# does not occur while SCK is low, the Hold mode ends on the next falling edge of CLK (non-
standard use) See
Figure 7.1
.
The SO output is high impedance, and the SI and SCK inputs are ignored (don’t care) for the duration of the
Hold mode.
CS# must remain low for the entire duration of the Hold mode to ensure that the device internal logic remains
unchanged. If CS# goes high while the device is in the Hold mode, the internal logic is reset. To prevent the
device from reverting to the Hold mode when device communication is resumed, HOLD# must be held high,
followed by driving CS# low.
Table 7.1
S25FL008A Protected Area Sizes
Status Register
Block Protect Bits
Memory Array
Protected
Portion of
Total Memory
Area
BP2
BP1
BP0
Protected
Address Range
Protected
Sectors
Unprotected
Address Range
Unprotected
Sectors
0
0
0
None
(0)
00000h–FFFFFh
SA15:SA0
0
0
0
1
F0000h–FFFFFh
(1) SA15
00000h–EFFFFh
SA14:SA0
1/16
0
1
0
E0000h–FFFFFh
(2) SA15:SA14
00000h–DFFFFh
SA13:SA0
1/8
0
1
1
C0000h–FFFFFh
(4) SA15:SA12
00000h–BFFFFh
SA11:SA0
1/4
1
0
0
80000h–FFFFFh
(8) SA15:SA8
00000h–7FFFFh
SA7:SA0
1/2
1
0
1
00000h–FFFFFh
(16) SA15:SA0
None
None
All
1
1
0
00000h–FFFFFh
(16) SA15:SA0
None
None
All
1
1
1
00000h–FFFFFh
(16) SA15:SA0
None
None
All
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