參數(shù)資料
型號: S25FL004AOLNFI000
廠商: Spansion Inc.
英文描述: 4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface
中文描述: 4兆位閃存的CMOS 3.0伏,50赫茲SPI總線接口內(nèi)存
文件頁數(shù): 17/39頁
文件大?。?/td> 945K
代理商: S25FL004AOLNFI000
March 28, 2005 S25FL004A_00_A1
S25FL Family (Serial Peripheral Interface) S25FL004A
15
A d v a n c e I n f o r m a t i o n
Table 4. Instruction Set
Write Enable (WREN)
The Write Enable (WREN) instruction (
Figure 4
) sets the Write Enable Latch
(WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Pro-
gram (PP), Erase (SE or BE) and Write Status Register (WRSR) instruction. The
Write Enable (WREN) instruction is entered by driving Chip Select (CS#) Low,
sending the instruction code, and then driving Chip Select (CS#) High.
Figure 4. Write Enable (WREN) Instruction Sequence
Instruction
Description
One-Byte Instruction
Code
Status Register Operations
06H (0000 0110)
04H (0000 0100)
05H (0000 0101)
01H (0000 0001)
Read Operations
03H (0000 0011)
0BH (0000 1011)
9FH (1001 1111)
Erase Operations
D8H (1101 1000)
C7H (1100 0111)
Program Operations
02H (0000 0010)
Deep Power Down Savings Mode Operations
Deep Power Down
Release from Deep Power Down
Release from Deep Power Down and
Read Electronic Signature
Address
Bytes
Dummy
Byte
Data Bytes
WREN
WRDI
RDSR
WRSR
Write Enable
Write Disable
Read from Status Register
Write to Status Register
0
0
0
0
0
0
0
0
0
0
1 to Infinity
1
READ
Read Data Bytes
3
3
0
0
1
0
1 to Infinity
1 to Infinity
1 to 3
FAST_READ
RDID
Read Data Bytes at Higher Speed
Read Identification
SE
BE
Sector Erase
Bulk (Chip) Erase
3
0
0
0
0
0
PP
Page Program
3
0
1 to 256
DP
B9H (1011 1001)
ABH (1010 1011)
0
0
0
0
0
0
RES
ABH (1010 1011)
0
3
1 to Infinity
CS#
SCK
SI
SO
High Impedance
Instruction
0 1
2
3
4
5 6
7
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