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參數(shù)資料
| 型號： | S25FL001D0FNAI013 |
| 廠商： | Spansion Inc. |
| 英文描述： | 2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface |
| 中文描述： | 2兆位，1兆閃存的CMOS 3.0伏，25兆赫的SPI總線接口內(nèi)存 |
| 文件頁數(shù)： | 26/38頁 |
| 文件大?。?/td> | 488K |
| 代理商： | S25FL001D0FNAI013 |
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26
S25FL Family (Serial Peripheral Interface)
30167A+1 June 9, 2004
P r e l i m i n a r y I n f o r m a t i o n
Power-up and Power-down
The device must not be selected at power-up or power-down (that is, CS# must
follow the voltage applied on V
CC
) until V
CC
reaches the minimum correct value,
as follows:
V
CC
(min) at power-up, and then for a further delay of t
PU
(as described in
Table
7
)
V
SS
at power-down
A simple pull-up resistor on Chip Select (CS#) can usually be used to insure safe
and proper power-up and power-down. To avoid data corruption and inadvertent
write operations during power up, a Power On Reset (POR) circuit is included. The
logic inside the device is held reset while V
CC
is less than the POR threshold value
(V
POR
). All operations are disabled, and the device does not respond to any
instructions.
The device ignores all instructions until a time delay of t
PU
(as described in Table
7
) has elapsed after the moment that V
CC
rises above the minimum V
CC
thresh-
old. However, correct operation of the device is not guaranteed if by this time V
CC
is still below V
CC
(min). No Read, Write Status Register, Program or Erase instruc-
tions should be sent until t
PU
after V
CC
reaches the minimum V
CC
threshold.
At power-up, the device is in Standby mode (not Software Protect mode) and the
WEL bit is reset.
Normal precautions must be taken for supply rail decoupling to stabilize the V
CC
feed. Each device in a system should have the V
CC
rail decoupled by a suitable
capacitor close to the package pins (this capacitor is generally of the order of 0.1
μF).
At power-down, when V
CC
drops from the operating voltage to below the mini-
mum V
CC
threshold, all operations are disabled and the device does not respond
to any instructions. (The designer needs to be aware that if a power-down occurs
while a Write, Program or Erase cycle is in progress, data corruption can result.)
Figure 17. Power-Up Timing
VCC
VCC (max)
VCC (min)
*Note:
Program, Erase, and Write Commands are not allowed and are not recommended during this period,
as the state of the device operation is unknown during tPU.
Device fully
accessible
time
tPU
VPOR
Reset State of the Device
*Note
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| S25FL001D0FNFI001 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface |
| S25FL001D0FNFI003 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface |
| S25FL001D0FNFI011 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface |
| S25FL001D0FNFI013 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface |
| S25FL002D | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface |
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