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參數(shù)資料
| 型號： | S25FL001D0FNAI013 |
| 廠商： | Spansion Inc. |
| 英文描述： | 2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface |
| 中文描述： | 2兆位，1兆閃存的CMOS 3.0伏，25兆赫的SPI總線接口內(nèi)存 |
| 文件頁數(shù)： | 14/38頁 |
| 文件大?。?/td> | 488K |
| 代理商： | S25FL001D0FNAI013 |
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14
S25FL Family (Serial Peripheral Interface)
30167A+1 June 9, 2004
P r e l i m i n a r y I n f o r m a t i o n
Write Enable (WREN)
The Write Enable (WREN) instruction (
Figure 4
) sets the Write Enable Latch (WEL)
bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program
(PP), Erase (SE or BE) and Write Status Register (WRSR) instruction. The Write
Enable (WREN) instruction is entered by driving Chip Select (CS#) Low, sending
the instruction code, and then driving Chip Select (CS#) High.
Figure 4. Write Enable (WREN) Instruction Sequence
Write Disable (WRDI)
The Write Disable (WRDI) instruction (
Figure 5
) resets the Write Enable Latch
(WEL) bit. The Write Disable (WRDI) instruction is entered by driving Chip Select
(CS#) Low, sending the instruction code, and then driving Chip Select (CS#)
High.
The Write Enable Latch (WEL) bit is reset under the following conditions:
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Page Program (PP) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
Figure 5. Write Disable (WRDI) Instruction Sequence
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be
read. The Status Register may be read at any time, even while a Program, Erase,
or Write Status Register cycle is in progress. When one of these cycles is in
progress, it is recommended to check the Write In Progress (WIP) bit before
CS#
SCK
SI
SO
High Impedance
Instruction
0 1
2
3
4
5 6
7
0
1 2
3 4 5
6 7
SCK
SI
SO
High Impedance
Instruction
CS#
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| S25FL001D0FNFI001 | 2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface |
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| S2516MH | SCR |
| S29GL032A30FFI012 | 64 Megabit, 32 Megabit, and 16 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology |
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S25FL001D0FNFI001 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface |
| S25FL001D0FNFI003 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface |
| S25FL001D0FNFI011 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface |
| S25FL001D0FNFI013 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface |
| S25FL002D | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface |
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