參數(shù)資料
型號： S25FL001D0FNAI013
廠商： Spansion Inc.
英文描述： 2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface
中文描述： 2兆位，1兆閃存的CMOS 3.0伏，25兆赫的SPI總線接口內(nèi)存
文件頁數(shù)： 18/38頁
文件大?。?/td> 488K
代理商： S25FL001D0FNAI013
18
S25FL Family (Serial Peripheral Interface)
30167A+1 June 9, 2004
P r e l i m i n a r y I n f o r m a t i o n
shifted out on Serial Data Output (SO), each bit being shifted out, at a frequency
f
SCK
, during the falling edge of Serial Clock (SCK).
The instruction sequence is shown in
Figure 9
. The first byte addressed can be at
any location. The address is automatically incremented to the next higher ad-
dress after each byte of data is shifted out. The whole memory can, therefore, be
read with a single Read Data Bytes (READ) instruction. When the highest address
is reached, the address counter rolls over to 00000h, allowing the read sequence
to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select
(CS#) High. Chip Select (CS#) can be driven High at any time during data output.
Any Read Data Bytes (READ) instruction, while a Program, Erase, or Write cycle
is in progress, is rejected without having any effect on the cycle that is in
progress.
Figure 9. Read Data Bytes (READ) Instruction Sequence
Read Data Bytes at Higher Speed (FAST_READ)
The Fast Read (FAST_READ) instruction implemented in this device is compatible
with industry standard Fast Read (FAST_READ) operations. The device is first se-
lected by driving Chip Select (CS#) Low. The instruction code for (FAST_READ)
instruction is followed by a 3-byte address (A23-A0 for 2Mbit devices) and a
dummy byte, each bit being latched-in during the rising edge of Serial Clock
(SCK). Then the memory contents, at that address, are shifted out on Serial Data
Output (SO), each bit being shifted out, at a maximum frequency F
SCK
, during
the falling edge of Serial Clock (SCK).
The instruction sequence is shown in
Figure 10
. The first byte addressed can be
at any location. The address is automatically incremented to the next higher ad-
dress after each byte of data is shifted out. The whole memory can, therefore, be
read with a single (FAST_READ) instruction. When the highest address is
reached, the address counter rolls over to 00000h, allowing the read sequence to
be continued indefinitely.
The (FAST_READ) instruction is terminated by driving Chip Select (CS#) High.
Chip Select (CS#) can be driven High at any time during data output. Any
Instruction
24-Bit Address
High Impedance
MSB
MSB
Data Out 1
Data Out 2
0
31
32
33
34
35 36
37 38 39
30
23
28
10
9
8
7
6
5
4
3
2
1
7
6
5
23
22 21
4
3 2
1
0
3
2
1
0
7
SO
SI
SCK
CS#
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