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參數(shù)資料
| 型號： | S1C63466F |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, QFP8-144 |
| 文件頁數(shù)： | 116/135頁 |
| 文件大?。?/td> | 1053K |
| 代理商： | S1C63466F |
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S1C63466 TECHNICAL MANUAL
EPSON
73
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
FCSEL: Timer 0 function selection register (FFC0HD1)
Selects whether the noise rejector of the clock input circuit will be used or not in the event counter mode.
When "1" is written: With noise rejecter
When "0" is written: Without noise rejecter
Reading: Valid
When "1" is written to the FCSEL register, the noise rejecter is used and counting is done by an external
clock (K13) with 0.98 msec* or more pulse width. The noise rejecter allows the counter to input the clock
at the second falling edge of the internal 2,048 Hz* signal after changing the input level of the K13 input
port terminal. Consequently, the pulse width of noise that can reliably be rejected is 0.48 msec* or less.
(
: fOSC1 = 32.768 kHz).
When "0" is written to the FCSEL register, the noise rejector is not used and the counting is done directly
by an external clock input to the K13 input port terminal.
Setting of this register is effective only when timer 0 is used in the event counter mode.
At initial reset, this register is set to "0".
PLPOL: Timer 0 pulse polarity selection register (FFC0HD0)
Selects the count pulse polarity in the event counter mode.
When "1" is written: Rising edge
When "0" is written: Falling edge
Reading: Valid
The count timing in the event counter mode (timer 0) is selected from either the falling edge of the
external clock input to the K13 input port terminal or the rising edge. When "0" is written to the PLPOL
register, the falling edge is selected and when "1" is written, the rising edge is selected.
Setting of this register is effective only when timer 0 is used in the event counter mode.
At initial reset, this register is set to "0".
RLD00–RLD07: Timer 0 reload data register (FFC4H, FFC5H)
RLD10–RLD17: Timer 1 reload data register (FFC6H, FFC7H)
Sets the initial value for the counter.
The reload data written in this register is loaded to the respective counters. The counter counts down
using the data as the initial value for counting.
Reload data is loaded to the counter when the counter is reset by writing "1" to the PTRST0 or PTRST1
register, or when counter underflow occurs.
At initial reset, these registers are set to "00H".
PTD00–PTD07: Timer 0 counter data (FFC8H, FFC9H)
PTD10–PTD17: Timer 1 counter data (FFCAH, FFCBH)
Count data in the programmable timer can be read from these latches.
The low-order 4 bits of the count data in timer 0 can be read from PTD00–PTD03, and the high-order data
can be read from PTD04–PTD07. Similarly, for timer 1, the low-order 4 bits can be read from PTD10–
PTD13, and the high-order data can be read from PTD14–PTD17.
Since the high-order 4 bits are held by reading the low-order 4 bits, be sure to read the low-order 4 bits
first.
Since these latches are exclusively for reading, the writing operation is invalid.
At initial reset, these counter data are set to "00H".
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