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參數(shù)資料
| 型號： | S1C63455F |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PQFP128 |
| 封裝： | PLASTIC, QFP5-128 |
| 文件頁數(shù)： | 81/119頁 |
| 文件大?。?/td> | 865K |
| 代理商： | S1C63455F |
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56
EPSON
S1C63455 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
4.10.2 Setting of initial value and counting down
Timers 0 and 1 each have a down counter and reload data register.
The reload data registers RLD00–RLD07 (timer 0) and RLD10–RLD17 (timer 1) are used to set the initial
value to the down counter.
By writing "1" to the timer reset bit PTRST0 (timer 0) or PTRST1 (timer 1), the down counter loads the
initial value set in the reload register RLD. Therefore, down-counting is executed from the stored initial
value by the input clock.
The registers PTRUN0 (timer 0) and PTRUN1 (timer 1) are provided to control the RUN/STOP for timers
0 and 1. By writing "1" to the register after presetting the reload data to the down counter, the down
counter starts counting down. Writing "0" stops the input count clock and the down counter stops
counting. This control (RUN/STOP) does not affect the counter data. The counter maintains its data
while stopped, and can restart counting continuing from that data.
The counter data can be read via the data buffers PTD00–PTD07 (timer 0) and PTD10–PTD17 (timer 1) in
optional timing. However, the counter has the data hold function the same as the clock timer, that holds
the high-order data when the low-order data is read in order to prevent the borrowing operation between
low- and high-order reading, therefore be sure to read the low-order data first.
The counter reloads the initial value set in the reload data register RLD when an underflow occurs
through the count down. It continues counting down from the initial value after reloading.
In addition to reloading the counter, this underflow signal controls the interrupt generation, pulse (TOUT
signal) output and clock supplying to the serial interface.
PTRUN0 (1)
PTRST0 (1)
RLD00–07 (10–17)
Input clock
PTD07 (17)
PTD06 (16)
PTD05 (15)
PTD04 (14)
PTD03 (13)
PTD02 (12)
PTD01 (11)
PTD00 (10)
A6H
F3H
Preset
Reload &
Interrupt generation
Fig. 4.10.2.1 Basic operation timing of down counter
Note: The counter mode selection register EVCNT should be set to "0" when timer 0 is used as a down
counter. Otherwise it will cause malfunction.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| S1C63557D04Q000 | 制造商:Seiko Instruments Inc (SII) 功能描述:EPSON MCU 4BIT |
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